應用於智慧型標籤基站接收機之數位訊號處理與架構設計

Digital Signal Processing and Architecture Design of Smart Badge Access Point Receiver

林文一(Wen-Yi Lin)

指導教授 ： 曹恒偉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.00070

摘要

本論文自訂了應用於短距離通訊的智慧型標籤(Smart Badge)系統，此智慧型標籤間是以無線通訊方式傳輸，通道規格採用不須授權的生醫通訊傳輸頻帶，整合傳送接收機於400MHz的通道，傳輸的調變方式採用架構較簡化的差分正交相移鍵控(Differential Quadrature Phase Shift Keying, DQPSK)，由於智慧型標籤在電路設計技術上注重省電與長時間的使用，可能會導致載波頻率及時脈的不精準，因而數位接收機端的設計需容忍較大的誤差。

論文中設計了用於短距離傳輸的智慧型標籤數位基站接收機，以低功耗與低複雜度架構為主要設計考量，在適當分析每個區塊所適用的定點位元點數後，實現了降頻428倍且低失真的降頻系統，將中頻訊號轉至基頻作數位訊號處理，且具備偵測並補償±500ppm的載波頻率飄移與符元時脈的誤差，並回傳符元振幅強度供自動增益控制電路調整類比轉數位器動態範圍，定點數錯誤率模擬在E_b/N_0為12dB時可達4×〖10〗^(-5)，與浮點數模擬相差0.3dB。硬體實現使用了國家晶片中心所提供的台積90nm製程，經完整佈局繞線後的晶片能操作在規格要求的42.8MHz，核心面積為0.3mm^2，面積利用率為68.7%，而功耗為11.7mW。

關鍵字

數位訊號處理 ； 數位降頻 ； 低複雜度 ； 架構設計 ； 接收機

並列摘要

In this thesis we propose a short-distance communication Smart Badge system which communicates through wireless channel and integrates the transceiver into licensed-free 400MHz bands. Modulation format of Smart Badge is DQPSK due to simplicity. The circuit design of Smart Badge is focusing on power saving and long standby time, so it may result in inaccurate carrier frequency and clock frequency, and the receiver is required to tolerate larger offsets.

This thesis designs and implements a Smart Badge base station receiver and takes low complexity and low power consumption into main considerations. It achieves a low distortion digital down conversion with down sampling by 428 and transfers the IF signal to baseband for digital signal processing. The receiver has the abilities to detect and compensate max. ±500ppm carrier frequency and clock frequency offset, and also returns amplitude of symbols for automatic gain control circuit to adjust the dynamic range of ADC. BER of fixed-point simulation is 4×〖10〗^(-5)at E_b/N_0=12dB, and the difference between floating-point simulation is less than 0.3dB. Hardware implementation and simulation use TSMC 90nm process offered by CIC, and the receiver after full auto place and route(APR) can operate at 42.8MHz with 0.3mm^2core area and 68.7% area utilization, and the power consumption is 11.7mW.

並列關鍵字

digital signal processing ； digital down conversion ； low complexity ； architecture design ； receiver

參考文獻

[5]M.G. Jimenez, V. Reyes and G. Dolecek, "Sharpening of Non-recursive Comb Decimation Structure," International Symposium on Communications and Information Technologies (ISCIT), pp. 458-463, Sept. 2013.

[6]G. Dolecek and S. Mitra, "A New Two-Stage Sharpened Comb Decimator," IEEE Transaction on Circuits System I, pp. 1414-1420, 2005.

[3]V. Papamichael, C. Soras and V. Makios, "FDTD Modeling and Characterization of the Indoor Radio Propagation Channel in the 434 MHz ISM Band," Applied Electromagnetics and Communications, pp. 217-220, Oct. 2003.

April 2007.

[7]T. Saramaki, T. Karema, T. Ritoniemi and H. Tenhunen, "Multiplier-Free Decimator Algorithms for Superresolution Oversampled Converters," Proc. IEEE International Symposium on Circuits and Systems, pp. 3275-3278, May 1990.