採用統計型時間數位轉換器的全數位頻率合成器

An All-Digital Frequency Synthesizer with Statistic TDC

鍾昀融(Yun-Rong Chung)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10029

摘要

本論文提出創新的採用統計型時間數位轉換器的全數位頻率合成器，統計型時間數位轉換器由全數位的方式實現，透過數學的統計運算能突破製程提供的最小時間解析度—單一個反相器的時間延遲，並免去類比架構設計上達到高解析度需要的複雜匹配。並且若不考慮面積和功耗的情況下，根據數學模型推論可以依要求幾乎無限制的提高時間解析度直到應用所需要的量級。
全數位頻率合成器採用了本論文提出的統計型時間數位轉換器、以及動態改變濾波係數的迴路濾波器、和加速鎖定的鎖定狀態控制電路。設計頻道為ISM的2.4億赫茲頻帶的14個頻道，模擬結果各頻道的鎖定時間均在8微秒之內，而鎖定狀態下的頻率誤差都在1百萬分之一之內。

關鍵字

統計型時間數位轉換器 ； 全數位頻率合成器 ； 動態迴路濾波器 ； 快速鎖定

並列摘要

In this thesis, an all-digital frequency synthesizer by utilizing novel technique of statistic time-to-digital converter (statistic TDC) is proposed. The proposed statistic TDC applies statistic properties of counters and associated toggle logics. Based on derived statistic model and system architecture, ultra high resolution of the converter is achieved. The minimum resolution can be even smaller than the minimum gate delay of inverter chains available in a process technology. Also, due to intrinsic statistical property, the statistic TDC reveals fully insensitive characteristics against device/process variations of fabrication technology. Therefore, design complexity of matching circuits required in analog converter design can be avoided. According to derived mathematical model, the minimum resolution of proposed statistic TDC can achieve almost unlimited order of magnitude, without considering area and power consumption.
The all-digital frequency synthesizer consists of a statistic TDC, a dynamic loop filter, and a high speed locking stage controller. The results of locking time simulation shows that settling time of all 14 channels in ISM 2.4 GHz band are all within 8μs and frequency errors of 14 channels under locking condition are all less than 1ppm.

並列關鍵字

Statistic TDC ； ADPLL ； Dynamic Loop Filter ； Fast Locking Technique

參考文獻

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