考慮非整數倍數高度之標準元件擺置

Non-Integer Multiple-Cell-Height Placement

林子堯(Zih-Yao Lin)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100474

摘要

非整數倍數高度電路 (non-integer multiple-cell-height designs) 對於同時考量面積、時序、能量消耗的電路最佳化而言，有更多的解答空間 (solution space) 和彈性。大的元件有較好的插針可存取性 (pin accessibility) 、較大的驅動力 (drive strengths) 、以及較小的延遲時間 (delay time) ；小的元件則有較小的面積 (area) 、較小的插針電容 (pin capacitance) 、以及較小的能量消耗 (power consumption) 。然而非整數倍數高度電路會產生額外的實體電路限制，並且當代工程工具仍無法在一個數位區塊 (digital block) 內完成非整數倍數高度之標準元件擺置，因此非整數倍數高度之標準元件擺置成為近年來實體設計領域的重要問題。
在本篇論文中，我們提出了基於列架構 (row) 的擺置流程來解決非整數倍數高度之標準元件擺置問題。我們的方法可以考量電路的元件高度分布將特定的列高度賦予到列上面，而後在擺置合法化 (legalization) 階段處理額外的實體電路限制，並且能有效率地同時考量元件位移將不同高度的元件擺置到對應的列上面。
實驗結果顯示，我們所提出的方法相較於先前的研究，可以有效地降低繞線線長 (routed wirelength) 以及整體能量消耗 (total power consumption) 並且得到更好的電路擺置結果。

關鍵字

實體設計 ； 電路擺置 ； 擺置合法化 ； 電路最佳化

並列摘要

A circuit design with non-integer multiple cell height (NIMCH) is more flexible for optimizing area, timing, and power simultaneously. Shorter cells have smaller areas, power, and pin capacitance with weaker drive strengths and lower pin accessibility and routability. Higher cells give larger drive strengths and better pin accessibility and routability at the costs of larger areas, power, and pin capacitance. Such NIMCH design must satisfy additional layout constraints that existing tool flows cannot handle well. In this thesis, we present a row-based algorithm for non-integer multiple-cell-height placement. Our algorithm consists of two main techniques: (1) a k-mean-based clustering method to assign heights to each row to define the regions of particular cell heights, and (2) a legalization method to move cells to satisfy NIMCH constraints. Experimental results show that our approach can significantly reduce the average routed wirelength and the average total power, compared with the state-of-the-art approach.

並列關鍵字

Physical Design ； Placement ； Legalization ； Circuit Optimization

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