邊緣採樣次鮑率之16-Gb/s數位時脈資料還原電路

A 16-Gb/s Edge-Based Sub-Baud-Rate CDR Circuit

黃文祈(Wen-Chi Huang)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200744

摘要

這篇論文提出了一個邊緣採樣次鮑率數位時脈資料還原電路。在四分之一速率的架構下，只須額外採用一被動高通濾波器作為微分器，即可將所需的時脈相位數量降至兩個，以節省電路消耗的功率。此外，本篇論文亦提出了補償延遲器來補償高通濾波器所固有的時間延遲，以改善抖動容忍度。此晶片使用台積電40奈米製程，操作在資料速度16 Gb/s且供給電壓1.2 V時的功耗僅23.2 mW，換算得功率係數為1.45 pJ/b。

關鍵字

次鮑率 ； 時脈資料還原器 ； 相位偵測器 ； 抖動容忍度

並列摘要

A 16-Gb/s edge-based sub-baud-rate digital clock and data recovery (CDR) circuit is presented in this thesis. By using a passive high-pass filter as a differentiator, only the complementary clocks are required for the quarter-rate implementation, which saves the power. To improve the jitter tolerance, the intrinsic delay of the high-pass filter is compensated by using compensation delay cells. The proposed sub-baud-rate CDR circuit is fabricated in 40-nm CMOS technology. Its power is 23.2mW for a supply of 1.2V at the data rate of 16 Gb/s. The calculated energy efficiency of this CDR circuit is 1.45 pJ/b.

並列關鍵字

sub-baud-rate ； clock and data recovery ； phase detector ； jitter tolerance

參考文獻

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