一個快速鎖定之倍頻延遲鎖定迴路

A Fast-Locking Multiplying Delay-Locked Loop

趙晏榆(Yen-Yu Chao)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100549

摘要

本論文實現一個快速鎖定以及抗諧波之倍頻延遲鎖定迴路。透過使用一個相位偵測器附帶選擇邏輯電路，此倍頻延遲鎖定迴路將可以抗諧波鎖定。透過使用快速鎖定電路後，當除頻器之除數由60切換至65，此倍頻延遲鎖定迴路之鎖定時間為295.77ns，約為8個參考時脈週期。這個倍頻延遲鎖定迴路使用台積電40奈米CMOS製程製作且其面積約為0.0088mm2。在供應電壓為1V下，其功率消耗為3.4mW，量測之參考突波為-45.1dBc，在1MHz偏移頻率下，量測之相位雜訊為-106.59dBc/Hz，且在輸出頻率1.5GHz時，量測之方均根抖動量為2.995ps。

關鍵字

快速鎖定 ； 抗諧波 ； 倍頻延遲鎖定迴路 ； 頻率偵測器

並列摘要

In this thesis, a fast-locking and anti-harmonic multiplying delay-locked loop (MDLL) is presented. By using the proposed phase detector with a select logic, the MDLL will be anti-harmonic. By using the fast-locking circuit, the locking time of the MDLL is 295.77ns around 8 reference clock cycles, while the division ratio is switched from 60 to 65. This MDLL is fabricated in a 40 nm CMOS process and its core area is 0.0088mm2. The power consumption of the MDLL is 3.4mW for a supply voltage of 1V. The measured reference spur is -45.1dBc. The measured phase noise is -106.59dBc/Hz at the offset frequency of 1MHz and the integrated rms jitter is 2.995ps at 1.5GHz.

並列關鍵字

fast-locking ； anti-harmonic ； multiplying delay-locked loop ； frequency detector

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