一個一百六十億位元每秒的線性等化器與具自適應時間0.3微秒的決策回授等化器

A 16-Gb/s Linear Equalizer and Decision-Feedback Equalizer With an Adaptation Time of 0.3us

詹銘軒(Ming-Xuan Zhan)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202202058

摘要

本論文實現一個資料傳輸速率為一百六十億位元每秒的線性等化器與具適應時間0.3微秒的決策回授等化器。藉由使用斜率偵測器切換符號-符號最小均方演算法的步長來達到快速收斂。以資料序列為PRBS7下的量測，通道衰減為-10.3dB到-24.3dB，資料錯誤率<10^-12。量測到的收斂時間小於0.3微秒。此等化器使用台積電40奈米製程製作，核心電路面積為0.179mm^2。最後，等化器的功率消耗為38毫瓦，達到的能量效率為0.098pJ/bit/dB。

關鍵字

連續時間線性等化器 ； 決策回授等化器 ； 符號-符號最小均方演算法

並列摘要

In this thesis, a 16-Gb/s linear equalizer and decision-feedback equalizer (DFE) using the proposed sign-sign least-mean-square (SSLMS) is presented. Using the slope detector to switch the step size of the SSLMS to achieve fast convergence. Measured with PRBS of 2^7–1, the bit error rates are all less than 10^-12 for channel loss from –10.3 to –24.3dB. The measured convergence time of the proposed SSLMS are determined within 0.3us. This equalizer circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.179 mm^2. Finally, the power consumption of the equalizers is 38mW, and the calculated energy efficiency is 0.098pJ/bit/dB.

並列關鍵字

Continuous-Time Linear Equalizer ； Decision-Feedback Equalizer ； Sign-Sign Least-Mean-Square

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