微波多層被動電路之佈局對電路檢查的後段：使用權重之電路比對

The back-end of layout vs. schematic checker for passive multilayer microwave circuit: schematic mapping using weights

邢恆瑞(Heng-Jui Hsing)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.00507

摘要

本篇論文提出了一種演算法來比對微波多層被動電路中電路圖網路表和佈局圖網路表的差異。根據節點相鄰的電感值和電容值來給予每個節點一個權重，再根據權重點進行節點配對。由於微波電路中元件的排列具有對稱性，可能會找到很多種可能性的配對，所以我們提出了一個評分的策略來找出最相似的配對組合。此演算法可比對電路圖網路表和從佈局圖萃取出來的網路表來幫助使用者驗證佈局圖，也可以指出在佈局圖網路表中缺少或是額外多出的元件來幫助使用者快速找到錯誤。

關鍵字

佈局圖 ； 網路表 ； 佈局圖對電路圖檢查

並列摘要

This paper presents an algorithm that can compare the net-lists between schematic and layout of passive microwave multi-layer circuits. Weight vectors that are related to inductance and capacitance of devices connected to a node are defined for node mapping. However, due to the symmetry of microwave circuits, many possible mapping may be found. We then developed a scoring policy to find the most similar mapping. This checker can help designers to verify layout by comparing the net-list from designer’s schematic and layout extracted net-list. This algorithm can also provide missing and extra components in net-list to assist designer to allocate layout errors quickly.

並列關鍵字

Layout ； net-list ； LVS

參考文獻

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