以數位蝕刻法應用於垂直式砷化銦奈米線之尺寸微縮及其場效電晶體之特性研究

在本論文中，我們探討數位蝕刻方法在垂直式砷化銦(InAs)奈米線的特性，並應用於垂直式砷化銦奈米線電晶體元件。砷化銦奈米線樣品是利用分子束磊晶(MBE)法在重摻雜之矽(111)基板上沿著[111]方向成長。成長後反覆利用氧電漿將奈米線表面氧化及利用醇類(alcohol- based)酸性蝕刻液將表面氧化層去除。透過此數位蝕刻的步驟，一次可以將砷化銦奈米線微縮半徑約2.9nm。最終我們完成直徑為40nm之垂直式砷化銦奈米線。在電晶體製作方面，我們透過原子層沉積(ALD)技術以及真空濺鍍系統(Sputter)分別成長閘極氧化層以及閘極金屬，接著採用low-k聚合物─苯環丁烯(BCB)作為平坦化材料及上下電極之間的間隔層，來有效地包覆住奈米線使其穩固垂直站立。隨後利用反應式離子蝕刻進行乾式蝕刻，蝕刻掉包覆於奈米線上半部之閘極金屬以定義閘極長度，同時露出奈米線頂端以利後續與上方電極形成歐姆接觸。接著以光學微影系統定義出上方電極位置並利用電子束蒸鍍機鍍上30nm鈦/100nm金。最後，我們直接以原先重摻雜之矽基板作為下方電極來完成垂直式砷化銦奈米線電晶體元件之製作。在電性量測上，我們成功製作出臨界電壓為-0.46V，且S.S.為137mV/decade的垂直式砷化銦奈米線電晶體，並將結果與文獻進行比較和討論。最後從文獻中探討未來該如何調整製程方向使砷化銦奈米線電晶體的電性能有進一步的提升。

關鍵字

數位蝕刻；氧化層飽和；砷化銦；垂直式奈米線；電晶體

並列摘要

In this thesis, we explore the characteristics of a digital etching method in vertical indium arsenide (InAs) nanowires and apply it to vertical InAs nanowire FETs. The InAs nanowires were grown along the [111] direction on heavily doped silicon (111) substrate using the molecular beam epitaxy (MBE) method. After MBE growth, the surface of nanowires was oxidized with oxygen plasma, and the oxide layer was removed with an alcohol-based etching solution. This method showed an etch rate of 2.9nm/cycle for InAs nanowires. Finally, we obtained vertical InAs nanowires with diameter down to about 40nm. In terms of transistor process, we used atomic layer deposition (ALD) technology and a sputtering system (sputter) to grow the gate oxide layer and gate metal, respectively. Then used low-k polymer-benzenecyclobutene (BCB) as the planarization material and spacer layer. Subsequently, reactive ion etching (RIE) is used to dry etch BCB and define gate length, the top of the nanowires is exposed at the same time in order to form ohmic contact with the upper electrode. Next, the pattern of the upper electrode was defined by an optical lithography system. The top electrode is composed of 30nm Ti / 100nm Au by electron beam evaporation to cover the NW tips. Finally, we directly used the heavily doped silicon substrate as the bottom electrode to complete the fabrication of the vertical InAs nanowire FETs. In electrical measurement, we have successfully demonstrated a vertical InAs nanowire FET with threshold voltage of -0.46V and a subthreshold swing (S.S.) of 137mV / decade. Finally, we compared the results with the literature and discussed how to modify the processing technologies to improve the electrical characteristics of nanowire FETs in the future.

並列關鍵字

Digital etching ； Oxide layer saturation ； InAs ； Vertical nanowire ； Field-effect transistors

參考文獻

[1] John Bardeen and Walter Brattain, "The Transistor, a SemiConductor Triode" Physical Review 74 pp. 230-231(1958).

Google Scholar

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