應用於2.4吉赫子多天線傳輸系統接收端之具空間干擾抑制力及本地振盪器的低功耗波束形成技術

Low-Power Beamforming Technology with Spatial Interferer Rejection and Integrated LO for 2.4-GHz MIMO Receivers

童耀新(Yao-Hsin Tung)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202101423

摘要

相位陣列電路可以提升SNR、提升空間線性度或者搭配MIMO應用進而增加資料傳輸速度，因此在5G以及未來的無線通訊技術中扮演重要的角色。因此，本論文分析相位陣列接收器設計考量，並利用CMOS 0.18-μm製程設計兩種不同的晶片。相位因子與訊號增益精準度和相位精準度有關，故本論文之相位陣列採用正交電壓相位合成方式實現相移以降低相位誤差。兩款晶片皆包含了本地振盪器、混頻器、基頻相移器與其他基頻電路。
相位雜訊在無線通訊系統中佔有重要的地位，因其與頻道間的線性度有關，是故本論文亦聚焦在低相位雜訊振盪器之探討，並提出了一個降低電感電容式正交振盪器相位雜訊的技巧，以及另一個針對環形振盪器在維持低相位雜訊的條件下對功耗做最佳化的設計技巧，振盪器量測結果顯示電感電容式正交振盪器的相位雜訊在1 MHz位移頻率為-126 dBc/Hz。
混頻器位於接收器前端，因此雜訊表現是關鍵，本論文分析並應用一個降低混頻器雜訊、高線性度的技巧，在第二款相位陣列晶片中達到混頻器量測結果：雜訊參數為10.3 dB，輸入端1 dB線性度為-5 dBm。除此之外，相位陣列改變場型的方式以及相位陣列中各個子電路的分析都涵蓋在本論文中。藉由第一款相位陣列模擬結果推算出空間干擾抑制為48 dB，第二款相位陣列量測結果則顯示34 dB的抑制。

關鍵詞：相位陣列、接收器、空間干擾抑制力、正交振盪器、混頻器、相位合成。

關鍵字

相位陣列 ； 接收器 ； 空間干擾抑制力 ； 正交振盪器 ； 混頻器 ； 相位合成

並列摘要

The phased array is one of the most crucial parts of the rising wireless communication industry. It can improve the SNR, enhance spatial linearity, and is available for MIMO usage to increase the data rate. Therefore, this thesis discusses a phased array receiver’s design considerations in CMOS 0.18-μm process, including two different IC implementations. The array factor is related to signal gain accuracy and phase accuracy. Hence, this thesis applies the vector-sum method to suppress the phase error. Both RF front-end receiver implementations consist of a local oscillator, mixers, baseband phase shifters, and other baseband circuits.
Phase noise plays a critical part in wireless communication because it relates to the linearity between channels. Consequently, this thesis also proposes a low phase noise LC-QVCO design technique and a power optimization method of a low-phase-noise ring oscillator. The oscillator’s measurement results show the phase noise of -126 dBc/Hz for LC-QVCO at 1-MHz offset frequency.
A mixer located at the front of a receiver should have a low noise figure. This thesis analyzes and applies a low noise and high linearity design technique in the second chip design to meet the measured performance with a noise figure of 10.3 dB, input-referred P1dB of -5 dBm. Moreover, this thesis covers some phased array synthesis methods and the analysis of each building block. The first phased array design is simulated to have a spatial interferer rejection of 48 dB, and the second design shows 34 dB rejection.

Keywords: beamforming, phased array, receiver, spatial interferer rejection, QVCO, mixer, vector-sum method.

並列關鍵字

beamforming ； phased array ； receiver ； spatial interferer rejection ； QVCO ； mixer ； vector-sum method

參考文獻

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