- 學位論文
應用於生醫感測系統之低功率低雜訊類比前端電路設計
Design of Low-Power Low-Noise Analog Front-End Circuits for Biomedical Applications
摘要
生理訊號感測在醫學臨床診斷上具有重要意義。以往生理訊號的量測皆須仰賴大型機台，拜科技進步之賜，現今的半導體工業已允許我們將整個系統微小化並實作於一個電路板，甚至是單一晶片上。將整個感測系統包含前端電路，類比數位轉換器，數位訊號處理器以及無線傳輸/接收模組全部整合在一個晶片內，是近幾年國際間熱門的研究課題。本論文著重於探討應用於此系統之類比前端電路設計。此電路必須將極其微弱且低頻的生理信號放大，去除來自外界與電路本身可能的雜訊干擾，同時亦要求低功率以滿足可攜式需求。 本論文實作並量測三個不同架構的晶片。三個架構皆為電容回授式儀表放大器。第一個架構成功量測出心電圖訊號，而未使用動態偏移補償技術的結果，導致電路閃爍雜訊影響了信號的品質。第二個架構在原本的放大器之中利用動態補償技術，以截波之方式達到去除閃爍雜訊的效果。此電路亦包含一個交換電容式低通濾波器以前饋補償的方式來去除因電極不匹配而造成電路失去功能。量測結果顯示電路具有高通濾波的效果，並成功去除電路之閃爍雜訊，然而因交換電容電路產生的雜訊堆疊影響了信號的品質。第三個架構改良於第二個架構，利用混合轉導電容濾波器以及切換電容的方式，在低功率的情況下成功實現了低雜訊。與前兩個架構相比，亦省下更多的電路面積。 此三個電路皆實作於台積電0.18微米製程。第一個晶片核心面積為0.67平方毫米，在1伏特的電源下消耗1.73微安培的電流，並達到14.69的雜訊效率指標(NEF)。第二個晶片核心面積為0.63平方毫米，在1.8伏特下消耗4.2微安培，NEF為 62.06。第三個晶片核心面積為0.42平方毫米，在1.8伏特下消耗2.27微安培，NEF為6.16。
並列摘要
The thesis presents the design of analog front-end circuits for biomedical applications. The analog-front-end circuit is the most critical building block in bio-potential monitoring SoC, since it should amplify very weak signals under noisy aggressors. The solutions to address these problems are described below: First, the front-end instrumentation amplifier should have HPF characteristics to filter out electrode offset. Second, the amplifier should achieve good balancing to resist 60Hz coupling from the mains. Finally, Dynamic Offset Cancelling (DOC) technique is usually used to cancel the effect of amplifier offset and in-band flicker noise. Three circuit architectures are implemented and the first two are verified, with the third chip under fabrication. All the chips employ capacitively-coupled instrument amplifier topology to achieve high power efficiency. The first chip used the architecture without chopper, and ECG waves are successfully measured. However, it suffers from flicker noise and parasitic capacitor trade-off problems. The second chip is implemented with chopper to get rid of flicker noise, with a ripple-reduction loop to suppress the output ripple caused by modulated offset. A switched-capacitor low-pass filter (SC-LPF) is employed to cancel the system input DC offset from electrode mismatch. The offset voltages and flicker noise are successfully moved out in measurement. However, due to the switching nature, the noise aliasing problem occurs when the SC-LPF is turned on. The Last chip is modified from the second one, instead of using a SC-LPF to cancel the electrode offset, a hybrid gm-C and SC architecture is used both to achieve area efficiency and low noise. The noise aliasing problem is greatly suppressed to the previous one. The first chip occupies 0.67 mm2 chip area and consumes 1.73-μA current from a 1-V supply. The NEF is 13.6 due to flicker noise problems. The second chip occupies 0.63 mm2 core chip area and consumes 2.1-μA current (4.2-μA with the SC-LPF) from a 1.8-V supply. It achieves a noise efficiency factor (NEF) of 4.29 when SC-LPF is turned off; and 62.06 when SC-LPF is turned on due to noise aliasing. The third chip occupies 0.42 mm2 area, drawing 2.1-μA from 1.8-V supply, and achieves 6.16 NEF with all the functions employed. All the chips are implemented with TSMC 0.18-μm process.
參考文獻
延伸閱讀
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