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  • 學位論文

超寬頻且低功耗的可變增益分散式放大器與毫米波放大器之研究

Researches on Ultra-Wideband Low-Power Consumption Variable Gain Distributed Amplifier and Millimeter-Wave Amplifiers

指導教授 : 王暉
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摘要


本論文提出了三個應用於微波及毫米波系統的關鍵放大器,其所使用的製程皆為90奈米互補式金氧半電晶體(CMOS FET)製程,第一個為低功耗且小晶片面積的高增益寬頻可變增益分散式放大器。第二個為創新且晶片核心面積小的變壓器匹配之無開關雙向功率低雜訊放大器。最後一個為應用於E頻帶的可變增益低雜訊放大器。 首先提出的放大器以混和傳統分散式放大器(CDA)以及串接單級分散式放大器(CSSDA)為架構,並以疊接放大器(cascode amplifier)為其中的增益元件,再利用主動終端可變電阻(AVTR)來達到平坦增益度之可變增益分散式放大器。其中增益頻寬積(GBW product)、直流功耗、增益控制範圍以及晶片面積為此可變增益分散式放大器的重要考量。在利用主動終端可變電阻的情形下,其增益平坦度可以做到有效的調整,且不會有增加直流功耗以及占用晶片面積之問題。此可變增益分散放大器達到21 dB的小訊號增益、40 GHz的3-dB頻寬以及18 dB的增益控制範圍,且直流功耗在最高的增益狀態僅有32.9 mW,而晶片的總面積只有0.72平方毫米。 接著是設計於Ka頻段基於變壓器架構之無開關雙向功率低雜訊放大器(switchless bidirectional PA-LNA),其採用了創新的雙向變壓器匹配網路來達到虛擬開關(virtual switch)之效果,以取代傳統的單刀雙擲開關(SPDT switch)電路,如此一來不僅能保有功率放大器以及低雜訊放大器原有之特性,還可以達到節省晶片面積之效果。此功率低雜訊放大器在功率放大器模式下達到18.1 dB的小訊號增益、9.5 GHz的3-dB頻寬以及在33 GHz的操作頻率下達到15.2 dBm的飽和輸出功率、29 %之最高功率附加效率。在低雜訊放大器模式下達到18.1 dB的小訊號增益、4.2 GHz的3-dB頻寬以及在35 GHz的操作頻率下達到最小4.5 dB的雜訊指數,而在3-dB頻寬下達到4.8 dB的平均雜訊指數。此晶片的核心面積只有0.21平方毫米。 最後提出的是應用於E頻段的可調增益低雜訊放大器,其電路由兩級的電流再利用(current-reused)架構串聯一級疊接放大器以及一級電流導引(current-steering)結構的放大器所組合而成。其中小訊號增益、直流功耗以及增益調控範圍為設計此放大器之考量。利用電流共享架構以及增益增強技術,此可調增益低雜訊放大器可以達到26.1 dB的小訊號增益和14.1 GHz的3-dB頻寬,在78 GHz的操作頻率下達到最小4.8 dB的雜訊指數以及17 dB的增益控制範圍,而在3-dB頻寬下達到5.4 dB的平均雜訊指數。此外其直流功率僅消耗23 mW且此晶片的整體面積只有0.52平方毫米。

並列摘要


This thesis proposes three essential amplifiers implemented in the 90-nm complementary metal oxide semiconductor (CMOS) FET process for microwave and millimeter-wave (mm-wave) systems. The first part is high-gain and wideband variable gain distributed amplifier (VGDA) with low power dissipation and small chip area. The second part is an innovative and small core area of the transformer (TF)-based switchless bidirectional power amplifier-low noise amplifier (PA-LNA). The last part is an E-band low-power consumption variable gain-low noise amplifier (VG-LNA). The first proposed amplifier is based on a conventional distributed amplifier (CDA) with cascaded single-stage distributed amplifier (CSSDA) in cascaded and employed cascode amplifier as the gain unit. Furthermore, the active variable termination resistor (AVTR) is adopted to achieve flat gain performance of VGDA. Among them, gain bandwidth product (GBW), dc power dissipation, gain control range, and chip area are important considerations for VGDA. In the case of using AVTR, its gain flatness can be effectively adjusted without increasing dc power consumption and occupying any additional chip area. This VGDA achieves a small-signal gain of 21-dB with a 40-GHz 3-dB bandwidth and 18-dB gain control range. The DC power consumption in the highest gain state is 32.9 mW and the total area of this chip is only 0.72 mm2. The second amplifier is the switchless bidirectional power amplifier-low noise amplifier (PA-LNA) designed in Ka-band based on TF architecture. The PA-LNA employs an innovative bidirectional TF matching network as the virtual switch to replace the traditional single-pole double-throw (SPDT) switch. As a side benefit, avoiding the use of the SPDT switches not only saves the chip area, but also maintains the original performance of PA and LNA modes. This PA-LNA achieves 18.1-dB peak small-signal gain in both PA and LNA modes. In the PA mode, it achieves the measured peak saturated output power (Psat) of 15.2 dBm with 29% peak power-added efficiency (PAEMAX) at 33 GHz, while LNA mode achieves a minimum noise figure of 4.5 dB at 35 GHz and an average noise figure of 4.8 dB in a 3-dB bandwidth. The core area of this chip is only 0.21 mm2. The last one is a variable gain-low noise amplifier (VG-LNA) applied to the E-band communication systems. This VG-LNA consists of a two-stage current-reused amplifier with a one-stage cascode amplifier and one-stage current-steering amplifier in cascaded. Among them, small-signal gain, dc power dissipation, and gain control range are main considerations for designing this amplifier. By adopting current-reused topology and gain enhancement techniques, this VG-LNA can achieve a 26.1-dB peak small-signal gain with 14.1-GHz 3-dB bandwidth, 17-dB gain control range, 4.8-dB minimum noise figure at 78 GHz, and an average noise figure of 5.4 dB in a 3-dB bandwidth. Besides, the power consumption is only 23 mW, and the total area of this chip is only 0.52 mm2.

參考文獻


[1] D. M. Pozar, Microwave Engineering, 3rd Ed. New York: Wiley, 1998.
[2] K. Chang, RF and Microwave Wireless Systems, New York: Wiley, 2000.
[3] FCC website [Online] https://www.fcc/gov/
[4] 3GPP website [Online] https://www.3gpp.org/
[5] Y. Wang et al, "A 39-GHz 64-element phased-Array transceiver with built-in phase and amplitude calibrations for large-array 5G NR in 65-nm CMOS," in IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 5, pp. 1249-1269, May 2020.

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