針對雙軌非同步電路的無時脈內建自測試

Clock-less BIST for Dual-rail Asynchronous Circuits

陳采婕(Tsai-Chieh Chen)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202000133

摘要

非同步電路由於其低功耗和耐變化特性而被廣泛用於現代超大型積體電路（VLSI）設計中。 這些現代設計通常在同一芯片上混合使用同步和非同步電路，這給測試帶來了挑戰。 在本論文中，我們提出了一種基於非同步電路掃描（A-scan）鎖存器的非同步內建自測試（A-BIST）。 A-scan是無需時脈的可測試設計（DFT），可以有效和無效訊號之間切換。 借助A-scan，我們的A-BIST是真正的無時脈全掃描設計。 實驗結果顯示，我們的面積成本和功耗成本分別比以前的同步版本30％和116％。 使用A-BIST，我們可以輕鬆地統合在同一芯片上的同步和非同步測試。

關鍵字

非同步電路 ； 雙軌邏輯 ； 低耗能測試 ； 內建自測試

並列摘要

Asynchronous circuits have been widely used in modern VLSI designs because of its low-power and variation-tolerant feature. These modern designs often mix synchronous and asynchronous cores on the same chip, which makes it a challenge in testing. In this paper, we propose an asynchronous Build-in Self Test (A-BIST), which is based on A-scan. A-scan is a truly clock-less DFT which can flip between Valid and Empty. With A-scan, our A-BIST is a truly clock-less and full-scan design. Experimental results show that our BIST area and power overhead is 30% and 116% smaller than previous synchronous counterpart, respectively. Using A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip.

並列關鍵字

Asynchronous circuit ； Dual-rail ； Low power test ； Build-in self test

參考文獻

[Akopyan 15] F. Akopyan, J. Sawada, A. Cassidy et al., “TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.10, pp. 1537–1557, 2015.

[Assadi 09] W. K. Al-Assadi and S. Kakarla, "Design for test of asynchronous NULL convention logic (NCL) circuits," J. Electron. Test., vol. 25, no. 1, pp. 117–126, 2009.

[Beigne 16] E. Beigné P. Vivet Y. Thonnart J. F. Christmann F. Clermidy, "Asynchronous circuit designs for the Internet of everything: A methodology for ultralow-power circuits with gals architecture" IEEE Solid-State Circuits Mag. vol. 8 no. 4 pp. 39-47 Nov. 2016.

[Chang 10] I. J. Chang, S. P. Park, K. Roy, "Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation", IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 401-410, 2010.

[Chang 13] K.-L. Chang, et al., "Synchronous-logic and asynchronous-logic 8051 microcontroller cores for realizing the internet of things: A comparative study on dynamic voltage scaling and variation effects." IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 3, no. 1, pp. 23–34, 2013.