使用門控延遲震盪器作積分器的循續漸進-增量式三角積分類比數位轉換器的分析與設計

Design and Analysis of a SAR-ISDM ADC with Gated-delay Oscillator Integrator

詹晏鈞(Yen-Chun Chan)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202000227

摘要

本篇論文提出一種單通道13 位元、五千萬赫茲取樣率的混合型兩階式類比數位轉換器。整個轉換器由10 位元的循續漸進式轉換器，加上4 位元的增量式三角積分轉換器所構成，扣除掉1 個冗餘位元，一共是13 位元。
本篇論文提出一種新的震盪器類型增量式三角積分類比數位轉換器的電路實現方法。循續漸進式轉換器的解析度往往受限於比較器的雜訊，使用增量式三角積分可以大幅減緩此一問題，但震盪器本身的非理想性又會對整體性能造成限制。本文提出的方法旨在解決現行方法使用之壓控震盪器的雜訊及不匹配問題，並且透過分析指出此一方法能使增量式三角積分轉換器能以更低的能量消耗，並且達到更高的解析度。
本篇論文指出原架構使用壓控震盪器的關鍵問題在於無法產生足夠大的增益/延遲。這會導致整個系統對於震盪器的雜訊及不匹配的容忍度降低，從而限制轉換器的解析度。本文提出的架構以門控延遲震盪器取而代之，將已經放大的時間訊號送入門控延遲震盪器進行積分，如此只要透過數位電路精準地控制訊號加入震盪器的時間點，可以達到比原架構高出10 倍以上的增益/時間。
本篇論文分為六個章節。第一、二章給出基本背景知識；第三章介紹整個提出電路及其建構塊的細節及架構；第四章針對提出電路做出詳細分析、比較且定量地分析數種降噪方法、比較不同數位降頻濾波器對於增量式三角積分降噪效果的差異、並且找出平均法量化雜訊及比較器雜訊的關係；第五、六章呈現量測結果及結論。

關鍵字

循序漸進式類比數位轉換器 ； 增量式三角積分 ； 高解析度 ； 時間數位轉換器

並列摘要

In this thesis, we present a single channel 13-bit 50-MS/s two-step analog-to-digital converter (ADC). The proposed hybrid ADC combines a 10-bit successive approximation register (SAR) ADC and a 4-bit Incremental-Sigma-Delta-Modulation (ISDM) ADC with one redundant bit. Overall, it is a 13-bit design.

In this thesis, we propose a new method to realize an oscillator-type ISDM. The resolution of SAR ADC is often limited by comparator noise. The ISDM architecture greatly relieved this problem, but the nonideality of the voltage-control oscillator (VCO) will degrade the overall accuracy. The main purpose of this thesis is to solve the noise and mismatch problem caused by VCO. Furthermore, it's proved by analysis and simulation that the proposed method can consume less power and reach higher resolution.

In this thesis, we indicate the critical problem of use of the VCO in the original architecture is that the VCO cannot produce enough gain/delay. The insufficient gain/delay will decrease the tolerance to noise and mismatch. The proposed architecture replaces the VCO with the gated-delay oscillator. We put amplified signal into the gated-delay oscillator and do the ISDM procedure. With digital timing control to stuff time signal into the oscillator, the proposed architecture can reach more than 10 times gain/cycle.

This thesis consists of six chapters. Chapter 1, 2 give the background knowledge; Chapter 3 introduces the architecture and all the building block of the proposed circuit in detail. Chapter 4 details the analysis of the proposed circuit, quantitatively compares and analyzes several noise reduction techniques, presents the performance difference of different digital decimation filter in ISDM, and finds the relation between quantization noise and comparator noise in the averaging method; Chapter 5, 6 present the measured result and conclusion.

並列關鍵字

SAR ADC ； Incremental-SDM ； high resolution ； Time-to-Digital Converter

參考文獻

[1] J. A. Fredenburg and M. P. Flynn, “A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2898–2904, Dec. 2012.

[2] S.-E. Hsieh and C.-C. Hsieh, “A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With

Opamp-Less Time-Domain Integrator,” IEEE J. Solid-State Circuits, vol. 54, no. 6, pp. 1648–1656, Jun. 2019.

[3] P. Harpe, E. Cantatore, and A. v. Roermund, “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” in ISSCC Dig. Tech. Papers, pp. 270–271, Feb. 2013.

[4] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang, L. Bu, and C.-C. Tsai, “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” in ISSCC Dig. Tech. Papers, pp. 386–387, Feb. 2010.