以交叉耦合可變電容補償之數位類比轉換器與佈局自動化

A Current-­Steering DAC with Cross­-Coupled Varactor Compensation Technique and Layout Automation

李昀翰(Yun-Han Lee)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100921

摘要

本論文內容探討以電流式數位類比轉換器為主。電流式數位類比轉換器由複數個相同的電流源組成，而電流源數量隨著解析度提高而呈指數增加，因此所有的電流源並聯容易導致輸出阻抗的不足。本論文提出一個改良的數位類比轉換器，目標是提升轉換器在高頻時的無雜散動態範圍表現(spurious-free dynamic range)。由於電流源具有輸出電容，且轉換器單位元的開關在導通時也帶有閘極-汲極寄生電容(Cgd)，這些電容對數位類比轉換器造成資料相依的輸出效應，因此降低了高頻的無雜散動態範圍，此論文提出的方法使用了交叉耦合可變電容來補償轉換器單位元的輸出電容，藉此減少在高頻時的資料相依電容效應。本篇論文實作了兩個六位元數位類比轉換器：其中一個為傳統式架構，另外一個為所提出之補償架構。實作晶片中另外內建了數位弦波資料產生器以降低量測工作複雜度。在二十億取樣頻率、信號頻率為三百六十八百萬赫茲下，傳統架構之轉換器的無雜散動態範圍表現(SFDR)為27.58分貝，補償架構之無雜散動態範圍表現(SFDR)則為32.04分貝，較傳統架構提升了約5分貝，其轉換器電源功耗為29.7毫瓦，傳統架構與補償架構之轉換器所占面積分別為0.162mm2與171mm2，只多了約6%。
另一方面，由於高解析度的數位類比轉換器會指數增加設計之複雜度，為解決此複雜度增加之設計難度，在此論文的後段將介紹一個新的電子設計自動化(EDA)技術——Analog Generator。其中，將介紹此技術之實作概念與其所自動化產生之電流源佈局成果。

關鍵字

數位類比轉換器 ； 高速 ； 資料相依 ； 交叉耦合 ； 電容 ； 補償 ； 佈局 ； 自動化

並列摘要

In this thesis, we focus on the current-steering digital-to-analog converters (DAC). The current-steering DAC is a monotonous architecture circuit that it consists of plural equivalent current cells. The number of current cells grows in exponential as the resolution increased. Thus, the total parallel impedance of all the current cells is hard to achieve enough output impedance. Here, we proposed an improved current-steering digital-to-analog converter, which aims at boosting the spurious-free dynamic range (SFDR) at high frequency. One of the restrictions of the bandwidth of DAC is code-dependent capacitance effect, contributed by output capacitance of current source and Cgd of switch while switch-on. We used cross-coupled varactor to compensate this code-dependent effect. In this work, two 6-bit DACs are implemented: one is the conventional architecture and the other is the proposed compensation architecture. Besides, a single-tone digital pattern generator is also implemented in the chip for measurement. At 2GS/s sample rate and 368MHz signal frequency, the SFDR of the conventional architecture is 27.58dB, and the SFDR of the proposed architecture achieves 32.04dB, improved about 5dB with respect to the conventional one. The power consumption of the proposed DAC is 29.7mW. The area of the two DACs are 0.162mm2 and 0.171mm2, where the proposed consumed only 6% more.
On the other hand, to relax the layout work of the large amount of current cells, a new EDA technology is introduced. "Analog Generator" aims at automizing the layout drawing and the simulation of circuit design. In the latter part of this thesis, the technology concept and the auto-created layout of a current source are presented.

並列關鍵字

Digital-­to-­analog converter ； High-speed ； Code-dependent ； Cross-coupled ； Capacitance ； Compensation ； Layout ； Automation

參考文獻

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