毫米波頻段鎖相迴路之設計與實現

Design and Implementation of Phase-Locked Loops in Millimeter-Wave Bands

蔡坤宏(Kun-Hung Tsai)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10825

摘要

隨著CMOS製程技術的發展與進步，使得低成本、低功率消耗、高速並應用於微波頻帶的通訊系統得以使用先進的CMOS製程來實現。舉列來說，在近年來，一些子電路應用在60GHz戶內高速資料傳輸、77GHz車用雷達及94GHz影像系統已被奈米級CMOS製程設計、實現並發表。在這些通訊系統中，鎖相迴路通常扮演重要的角色，像是提供本地振盪信號或是輸出參考脈波給系統做資料取樣。在微波頻帶中，雖然有一些鎖相路已被實作成功，但是，具有高輸出頻率、低功率且有低相位雜訊的鎖相迴路，對於電路設計者依然是一個具挑戰性的工作。
在本論文中，我們將重點放在操作頻率高於90GHz的鎖相迴路設計、分析與實現。在第一顆晶片中，我們設計一個低功率，操作在96GHz附近的鎖相迴路。在鎖相迴路中，我們適當地使用四種除頻器架構來設計除頻串以達到低功率消耗的目標。根據我們的量測結果，與先前發表的鎖相迴路比較來，此一除頻串可減少約50%的功率消耗。同時，我們也分析了除頻串中，第一級除頻器的操作範圍，並將分析的結果應用在電路設計上，以確保壓控振盪器之輸出頻率可與第一級除頻器對準。在鎖相迴路的閉迴路量測中，此一電路成功的鎖定在96GHz附近，且其功率消耗約為43.7mW。據我們所知，與先前的文獻比之，此一鎖相迴路具有最低的功率消耗。
在第二個晶片中，我們首先分析一個四階的LC共振腔電路。根據我們分析的結果，與傳統的並聯式LC共振腔電路比之，此一共振電路可達到84.7%的頻率提升。我們將此四階LC共振腔電路應用於壓控振盪器的製作並整合至鎖相迴路中，希望鎖相迴路產生高於100GHz頻率信號。根據我們的量測結果顯示，使用四階LC共振腔電路的壓控振盪器工作在103.057 到 104.581GHz間。同時，使用此壓控振盪器的鎖相迴路鎖定在103.058 至 104.58GHz.間。從此一晶片中，我們看到了使用CMOS製程設計高於100GHz脈波產生電路的可能性。此外，據我們所知，與其他的文獻相較之下，此一晶片是所有CMOS製程中，具有最高輸出頻率的鎖相迴路。

關鍵字

互補式金氧半導體 ； 毫米波 ； 鎖相迴路 ； 壓控振盪器

並列摘要

Due to the remarkable development in CMOS technology, it is possible to design low-cost, low-power, and high-speed communication systems in millimeter-wave (MMW) bands by advanced CMOS process. For example, the building blocks for 60GHz indoor high-speed data link, 77GHz automotive radar, and 94GHz imaging system have been realized in nanoscale CMOS technology. In these communication systems, phase-locked loops (PLLs) usually play important roles to serve as local oscillator (LO) for signal conversion or provide reference clock for data sampling procedure. In MMW applications, it is still a challenge work for circuit designer to develop PLLs with high operation frequency, low power consumption, and good phase noise performance.
In this dissertation, we focus on the design, analysis, and implementation of PLLs above 90GHz. For the first work, a low power 96GHz charge-pump PLL (CPPLL) is introduced. In the PLL, four divider topologies are adequately employed to the design of the divider chain, and the divider chain can save more than 50% power dissipation of published PLLs according to our measurement. Moreover, the operation range of the first divider in the divider chain is analyzed, and the results are applied to the circuit design to ensure robust frequency alignment between VCO and the first divider. From the closed-loop measurements, the PLL successfully locks near 96GHz and consumes 43.7mW (including output buffers) from 1.2/1.3V supply. To the best of author’s knowledge, this work has the lowest power consumption while compared to the published PLLs operating above 90GHz.
In the second work, a fourth-order LC resonator is introduced. According to our analysis, the fourth-order LC resonator has a higher resonant frequency, and a frequency improvement of 84.7% can be achieved while compared with the conventional parallel LC resonator. A VCO using the fourth-order resonator is realized to demonstrate its feasibility for circuit design. Moreover, the VCO is integrated into a CPPLL for the clock generation above 100GHz. According to the experimental results, the VCO oscillates from 103.057 to 104.581GHz, and the PLL with the VCO locks from 103.058 to 104.58GHz. This PLL demonstrates the possibility of clock generation above 100GHz in CMOS technology. To the best of author’s knowledge, it is currently the fastest PLL in all CMOS technologies.

並列關鍵字

CMOS ； Millimeter-Wave ； Phase-Locked Loop(PLL) ； Voltage-Controlled Oscillator(VCO)

參考文獻

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