使用寬範圍頻率偵測器與抖動容忍度增強技術的鮑率時脈資料還原電路

Baud-Rate Clock/Data Recovery Circuits with Wide-range FD and Jitter-Tolerance-Enhanced Technique

陳尉銘(Wei-Ming Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202101157

摘要

這篇論文的主題 主要分為兩個部分，第一部分實現了一個資料傳輸率為10.4-16-Gb/s無參考頻率之鮑率數位時脈資料還原電路與1-tap決策回授等化器。提出的寬範圍鮑率頻率偵測器由粗調頻率偵測器與細調頻率偵測器所組成。此寬範圍鮑率頻率偵測器、相位偵測器與決策回授等化器共用前級高速比較器，因此無需增加任何額外高速硬體成本。除此之外，透過偵測五位元之資料序列的取樣點移動，此細調頻率偵測器可以達到穩固的頻率偵測器與相位偵測器切換。此頻率偵測器不只達到寬的頻率鎖定範圍，同時具有短的頻率追鎖時間。此架構使用台積電40奈米製程製作，核心電路面積為0.1004mm^2，操作在資料速度16Gb/s的功率消耗為39.9mW，達到的能源效率為2.49pJ/b。
第二部分實現了一個抖動容忍度增強之數位鮑率時脈資料還原電路。為了改善時脈資料還原電路的抖動容忍度，此部分提出一背景校正電路。此晶片使用台積電40奈米製程，其核心電路面積為0.1mm^2。在 通道衰減為10.31dB@10GHz與輸入資料速度為20Gb/s資料序列為PRBS2^7-1下，資料錯誤率10^-12。 透過所提出的校正電路，此電路改善量測到的高頻抖動容忍度。量測到的收斂時間小於5微秒，操作在資料速度20Gb/s的功率消耗為55.4mW，達到的能源效率為2.77pJ/b 。

關鍵字

鮑率 ； 頻率偵測器 ； 抖動容忍度 ； 等化器 ； 時脈資料還原電路

並列摘要

This thesis consists of two parts. The first part implements a 10.4-16-Gb/s reference-less and baud-rate digital clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE). A wide-range baud-rate frequency detector (FD) is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five-bits data patterns, the FFD has a robust FD-to-PD transition. This FD not only achieves a wide frequency capture range, but also has a short frequency settling time. This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm^2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b.
The second part implements a jitter-tolerance-enhanced digital baud-rate CDR. To improve the jitter tolerance (JTOL) of a CDR circuit, a background calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1mm2. For a channel loss of -10.31dB at 10GHz and a 20Gb/s PRBS of 2^7-1, the measured bit error rate is less than 10^-12. By the proposed calibration circuit, the measured high-frequency jitter tolerance is improved. The measured convergence time of the calibration circuit is less than 5μs. The power of this CDR circuit is 55.4mW at 20 Gb/s, and the calculated energy efficiency is 2.77pJ/b.

並列關鍵字

baud-rate ； frequency detector ； jitter tolerance ； equalizer ； clock/data recovery

參考文獻

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