以CMOS 0.18微米製程實現1伏特以時間為基礎之類比數位轉換器與線性電壓時序轉換電路

1 V Time-Domain-Based Self-Calibrated Analog-to-Digital Converter with Linear Voltage-to-Delay Circuits in 0.18-um CMOS Technology

楊承勳(Chung-Hsing Yang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.02908

摘要

本論文提出兩個內建自我校正功能之以時間為基礎的類比數位轉換器。藉由利用雙路徑延遲電路架構來校正非理想效應。提出一個線性的電壓時序轉換器以增加此TD-ADC的線性度。
這兩個晶片是以台積電點一八微米金氧半製程製作。第一個晶片消耗1.6毫安培，操作在1伏特供應電壓之下。取樣頻率是33千赫茲，可輸入之共模範圍從170毫伏特至310毫伏特。電路沒有missing code，電路面積是1.2 mm X 1.2 mm。第二個晶片消耗746.3微安培，操作在1伏特供應電壓之下。取樣頻率是400千赫茲，可輸入之共模範圍從200毫伏特至800毫伏特。當給定200千赫茲輸入頻率時，電路訊雜比是41 dB。面積是1.35 mm2。

關鍵字

類比數位轉換器 ； 延遲 ； 取樣保持電路 ； 數位類比轉換器 ； 連續漸進式 ； 線性

並列摘要

This thesis presents two time-domain-based analog-to-digital converters (TD-ADCs) with build-in calibration function. The proposed TD-ADCs utilize dual delay architecture to calibrate the non-idealities. A linear voltage-to-delay circuit is proposed to enhance the linearity of the TD-ADC.
Both chips are fabricated in TSMC 0.18 um CMOS process. The first chip consumes 1.6 mA from 1-V supply. The sampling rate is 33 kHz and input common range is from 170 mV to 310 mV. There is no missing code and the area is 1.2 mm by 1.2 mm. The second one consumes 746.3 uA from 1-V supply. The sampling rate is 400 kHz and input common mode range is from 200 mV to 800 mV. With 200 kHz input frequency, the SNR is 41 dB. The area is 1.35 mm by 1.35 mm.

並列關鍵字

analog-to-digital converter ； delay ； sample and hold ； digital-to-analog converter ； DAC ； successive approximation ； linear

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