引用差值產生器之切換電流式管線化類比數位轉換器設計

Design of the Switched-Current Pipelined Analog-to-Digital Converter Using Residue Generator

許仕杰(Shih-Chieh Shu)

指導教授 ： 宋國明

國立臺北科技大學/機電學院/機電整合研究所/碩士(2006年)

摘要

本論文主要研究重點在於切換電流式管線化類比數位轉換器之設計，文中探討之內容包含常用之類比數位轉換器架構與原理的介紹，以及對於欲設計之電路誤差補償與設計理論。而在內部系統設計上，將以電流訊號之切換為基礎，即利用MOS元件上的閘、源極間之寄生電容取代實體電容，以儲存資料，節省大量面積，每級採用之解析位元數為1.5位元。
論文中，我們提出一個取樣率可以達到50M-Samples/sec，而讓精確度提升的管線化類比數位轉換器。另外，在電路系統實現上，將引用一個新構想，取代傳統式管線化單級內部架構，透過所設計之差值產生器，可免除因DAC所造成之誤差。在採用 TSMC0.35 µm 2P4M製程來製作此晶片及取樣率為50MHz下，我們以輸入頻率1MHz的弦波訊號進行測試，其最大的訊號雜訊失真比可達到48dB，相對於解析度約7.5位元，而晶片於3.3V的供應電壓下，消耗功率約為160mW，微分非線性誤差(Differential Nonlinearity, DNL)<0.4 LSB, 積分非線性誤差(Integral Nonlinearity, INL)<0.8 LSB，晶片之核心面積約為0.66mmX0.68mm。

關鍵字

類比數位轉換器 ； 管線化類比數位轉換器 ； 取樣保持電路

並列摘要

The switched-current pipelined analog-to-digital converter is the main research in this paper. It includes not only the architectures and principles of the analog-to-digital converter, but also the occasions and the circuit compensations of the design topic. The internal system design based on the switched-current technique, which use gate parasitic capacitor instead of the physical capacitor, will decrease the chip area and enhance the entire system efficiency. Note that the fundamental circuit design will adopt the 1.5bits/stage technique.
Further more, the proposed pipelined ADC can achieve 50-Msample/s and increase the signal accuracy. That is, we’ll propose a new conception instead of the traditional pipelined ADC internal structure at the circuit system to eliminate the error by DAC. With the TSMC 0.35um 2P4M CMOS process and the sampling frequency of 50 MHz, the simulation is completed with a sine wave of 1MHz. The simulation results show that the signal to noise ratio is greater than 48dB (about 7.5 bits), the power consumption is about 160 mW with a 3.3V power supply, the DNL(Differential Nonlinearity)<0.4 LSB, and the INL(Integral Nonlinearity)<0.8LSB. Note that the core area is 0.66mmX0.68mm.

並列關鍵字

Analog-to-Digital Converter ； Pipelined ADC ； Sample and Hold

參考文獻

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