眾所皆知,節省電能的方式有兩種,一種為提高產品效率,而另一種為提高產品使用時之功率因數及降低諧波失眞。在電力電子的產品中,諧波電流也會影響功率因數。2001年,歐洲的國際電工委員會頒佈了IEC 61000-3-2諧波標準,正式對電子設備所產生之諧波有詳細的規範。於此標準中,規定凡輸出在75W以上之電子設備產品,都必須通過諧波測試,其方法為,以量測單一待測物對電力系統所產生的諧波干擾。雖然許多的主動式功率因數校正拓撲已經可把諧波失真降到很低,但由於存在著橋式整流二極體之順向壓降及橋式整流二極體後之高頻濾波電容,故輸入電流在輸入電壓零點附近仍會發生停頓及畸變之現象。因此,基於上述所言,本論文採用電壓疊加的方法,無須藉由調整輸入電流命令的相位或增加在零輸入電壓附近時之開關的導通時間,只需用少量的元件來改善輸入電流之零交越失真,即可降低其總諧波失真。
As generally acknowledged, energy saving has two methods. One is to upgrade the efficiency of the product; the other is to improve its power factor and reduce its harmonic distortion. In the power electronics product, the harmonic current affects the power factor and creates the undesired noise and the additional power loss. Therefore, the International Electrotechnical Commission (IEC) released IEC 6100-3-2 harmonics standards in 2001, and accordingly the harmonic limits were described in detail. In these standards, if the electronics product has the output power above 75W, the harmonic test is needed, which measures a single testing device so as to know how much the harmonics affect the power system. Although many active power factor correction topologies are presented to reduce the harmonic distortion to some extent, there still exists a common problem that the input current stops flowing and is distorted in the neighborhood of the zero input voltage. This is due to the forward voltages of the diodes in the bridge rectifier and the capacitor used to filter out high-frequency switching noises. In this study, based on the mention above, the voltage superposition is used without phase adjustment in the input current command and without enlarging the turn-on period of the switch in the vicinity of the zero input voltage, but only with a few components, so as to improve the zero-crossing distortion of the input current, thereby reducing the value of the total harmonic distortion.