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  • 學位論文

探討0.13微米製程之PMOS電晶體其熱載子可靠度在升溫下的變化

An Investigation on Hot Carrier Effect at Elevated Temperatures for pMOSFETs of 0.13μm Technology

指導教授 : 黃恆盛 教授 陳雙源 副教授

摘要


在矽的物理性質中,由於電洞的平均自由徑較短,約為電子的一半;電洞的載子遷移率較差,在室溫中約為電子的三分之一。因此過去皆認為,電洞較難形成撞擊離子化,亦較難產生interface states;故在前人的研究中,NMOS電晶體因熱載子所造成的特性衰退遠較PMOS電晶體嚴重。然而,在MOS電晶體進入深次微米及奈米製程後,上述的情況似乎已改變,PMOS電晶體的熱載子可靠度已成為一項新的問題。 在本研究中,我們用0.13微米製程,通道長度分別為90奈米與120奈米、氧化層厚度分別為20Å與32Å、寬度為10微米的PMOS電晶體做為實驗樣本,研究25℃、75℃、125℃,三種不同的溫度條件與(1)閘極電壓在基板電流最大值(2)閘極電壓等於汲極電壓等兩種不同偏壓組合下的熱載子可靠度,測試元件的衰退情形。研究結果發現,PMOS電晶體的熱載子機制已非由負氧化層電荷(negative oxide charge)主導;而在測試條件的組合中,又以高溫及閘極電壓等於汲極電壓的測試方式,電流衰退程度最為嚴重,此與傳統觀察的基板電流最大值為最嚴重衰退情形有所不同,故基板電流已無法完全反應熱載子的現象。比較幾種汲極的衰退程度中,又以類比電路的電流,Id,op的衰退最為嚴重,此警訊應值得設計類比電路的工程師參考。 除此之外,經與前人所做的NMOS電晶體熱載子可靠度研究互相比較,本研究發現P型的衰退程度與N型已不分軒輊,我們認為在往後探討熱載子的可靠度時,須將N型與P型電晶體合併討論。

關鍵字

熱載子 可靠度 溫度 數位電路

並列摘要


On the basis of the physical properties of silicon, the mean free path of holes is about one half of the electrons, and hole’s mobility is about one third of the electrons at the room temperature. Therefore, holes were considered harder to create interface states. The hot carrier inducing current degradation in nMOSFETs was considered much more severely than that in pMOSFETs. However, as the transistor channel length has been scaled down into deep submicron and nano regime, the previous concepts may not valid again and the hot carrier reliability of pMOSFETs has gradually become a significant issue. In this study, the tested devices were from 0.13 µm technology of UMC. The pMOSFETs used in this experiments have Lg= 90 nm with physical gate oxide thickness, 20Å (core devices) and Lg=120 nm with physical gate oxide thickness, 32Å (I/O devices), all with W=10 µm. Stress conditions were set at temperature 25 ℃, 75 ℃ and 125 ℃, and Vg biased at peak substrate current and maximum gate voltage as drain voltage. It is found that the pMOSFET’s hot carrier mechanism is no longer dominated by negative oxide charges. Comparing different stress modes, the stress with the maximum gate voltage and the higher temperature cause the most severe current degradation. As a result, peak substrate current may not directly indicate hot carrier effect anymore, which is inconsistent with the conventional concept. After comparing all the drain currents, it is found for first time that Id,op is the worst among three kinds of currents. Such message should be valuable for analog circuit designers to have their circuits exhibiting satisfactory reliability. Furthermore, we compared our results to our former investigation of hot carrier on nMOSFETs. It is found that the degradation of pMOSFETs is comparable to nMOSFETs. Hence, we can conclude that the hot carrier reliability of pMOSFETs is as serious as nMOSFETs.

並列關鍵字

Hot Carrier Reliability Temperature Digital Circuit

參考文獻


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被引用紀錄


Chen, Y. T. (2007). 利用模擬分析具環形及淺摻雜汲極佈植之90 nm nMOSFETs的Ion / Ioff [master's thesis, National Taipei University of Technology]. Airiti Library. https://doi.org/10.6841%2fNTUT.2007.00220

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