適用於3GPP LTE-A系統之頻率同步硬體設計與實現

Design and Implementation of Frequency Synchronization for 3GPP Long Term Evolution Advanced Systems

張少華(Shao-Hua Chang)

指導教授 ： 李宇軒

元智大學/電機通訊學院/電機工程學系/碩士(2013年)

https://doi.org/10.6838/YZU.2013.00154

摘要

本論文研製之在3GPP長期演進先進系統下的頻率同步設計。主要是設計基頻接收器在3GPP LTE-A下行傳輸時考慮快速衰落通道效應。基頻接收器包含的功能有同步與通道估測。在本論文中，當接收器啟動時，我設計了可以估測並補償殘留載波頻率偏移和取樣時脈偏移。本設計採用臺積電90 nm CMOS技術，在18.432 MHz的工作頻率。與其他頻率同步的設計相比，我們所提出的設計，其中只有利用位移相加的方法可以讓面積節省約15.0%，利用演算法改良的方式可以讓面積節省約50.0%，而整體可以節省約23.6％的面積和14.0％的功耗。

關鍵字

頻率同步 ； 長期演進技術升級版 ； 載波頻率偏移 ； 取樣時脈偏移 ； 同步

並列摘要

This research proposes a frequency synchronizer design for 3GPP Long Term Evolution Advanced (LTE-Advanced) Systems. The baseband receiver design for the 3GPP LTE-Advanced downlink systems is under fast-fading channels. The baseband receiver contains the two main function blocks of synchronization and channel estimation. In my study, when the receiver starts up, this thesis designed the estimation method for the residual carrier frequency offset and sampling clock offset. This design uses TSMC 90 nm CMOS technology at 18.432 MHz operating frequency. As compared with the designs of the frequency synchronizer, our proposed design only used shifts and adders can save the area cost about 15.0%; moreover, applying the algorithm improvement, We can save the cost about 50.0%.In the summary, we can save about 23.6% and 14.0% in the area and power as compared with the conventional designs.

並列關鍵字

Frequency Synchronization ； Long Term Evolution Advanced ； Carrier Frequency Offset ； Sampling Clock Offset ； Synchronization

參考文獻

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