Capture Power Reduction for At-Speed Scan-Based Testing Using Layout-Aware Location X-Filling

降低區塊間高速測試所消耗功率

林志偉(Chih-Wei Lin)

指導教授 ： 張慶元

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

With the rapid improvement of testing technique, the basic of testing function is a necessary technique. It also needs to reduce the testing time and power dissipation as well as testing cost. Nowadays, it is important to solve problem which is the more power dissipation during testing. The more power dissipation can cause the effect of IR-drop and hot-spots. The chip is easy to fail with the high power dissipation. Therefore, applying the concept of gate density, this thesis proposes two methods (Probable Weighted Switching Activity X-Fill, PWSA X-Fill; and Location-Aware X-Filling) to reduce the power dissipation and distributes the accumulated heat.
Applied in ISCAS-89 benchmark circuits (s9234, s13207, and s38417), the simulation results show that the original power is reduced about 10% peak and 20% average in the launch cycle and 9% peak and 12% average by the proposed x-fill methods. Compared with other x-filling, the proposed x-filling has better result on reducing launch and shift cycle power and would reduce the occurrence of IR-drop and hot-spots for at-speed scan-based testing.

關鍵字

消耗功率 ； 高速測試 ； 降低區塊間消耗功率

並列摘要

隨著晶片測試技術快速的提升下。在測試領域中，除了要求最為基本的測試功能外，還需要能達到降低測試時間、降低測試所消耗的功率以至於將成本耗損減少到最低，以得到最佳的測試效果。然而當前最為學者們所討論的是要如何在測試中降低測試功率的消耗。這是由於測試時有可能會造成過高的功率消耗，進而使得熱能不斷產生於晶片中不容易散去。如此，導致晶片內的溫度過高。相當容易使得晶片內的測試電路因燒毀而測試失敗。因此為了預防測試時所發生的熱損壞現象，本篇論文提出了一個測試填入方法。運用機率計算方法，計算預估出最為可能在電路邏輯運算完後出現0或1的機率，再填入適當的邏輯值。如此，不但能夠降低測試功率消耗還能分散熱能過度密集於某些區塊，以防止熱損壞的現象。並且還用密集程度去研究如何降低測試時所導致過熱的損壞情形。
本篇論文在高速測試環境下，所使用的測試電路為ISCAS-89中的標準電路，如s9234, s13207和s38417等電路。將比較於其他相關測試填入方法上，本論文所提的方法在觸發周期所消耗的功率可以減少大約10%的最大功率與大約20%的平均功率。在捕捉周期所消耗的功率可以減少大約9%的最大功率與大約12%的平均功率。除了在消耗功率可達到理想的降低外，本篇論文所提的方法在實驗數據上，皆能明顯有效的將過度密集的熱能區塊分散開來。以預防熱能過度集中而導致晶片在測試時燒壞現象，而提高測試的良率。

並列關鍵字

Capture Power Reduction ； At-Speed Scan-Based Testing ； X-Filling ； Layout-Aware Location X-Filling

參考文獻

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