應用敏感度分析於三維晶片內穿矽連接孔之特性研究

在現今製程技術不斷的進步下，一有限平面內所能擺放的電晶體個數終將因達到各元件所能容忍的最小尺寸而趨於飽和。三維晶片（3D IC）被認為可以有效的解決此一問題，透過在垂直方向堆疊多個平面藉以增加面積來給電晶體擺放。而這些垂直排列且互相平行的平面則是利用一種稱作穿矽連接孔（Through Silicon Via, TSV）的橋樑來進行彼此間的溝通。在製程上由於穿矽連接孔的良率不佳，致使三維晶片的總體良率下降，因此為了增進三維晶片的良率，我們有必要針對穿矽連接孔進行一連串的研究與測試，包含除錯、修復、建立其在真實晶片內延遲時間的分佈情況……等。在這篇論文中，我們提出了一個方法能測出在三維晶片內穿矽連接孔的延遲時間。我們採用了振盪環的概念，利用一些周邊電路與一對穿矽連接孔來形成一個振盪環。以此為基礎，我們使用了稱之為敏感度分析的方法來進一步推導出在振盪環裡每一根穿矽連接孔的延遲時間。我們藉由調控這二根穿矽連接孔驅動端的驅動力道來使振盪環振出來的週期發生改變，接著我們再量測這些變動量並經由一些分析來得出每一根穿矽連接孔的延遲時間。我們同時也提出測量多對穿矽連接孔的方法，此種方法能夠解決在測試中需要同步訊號的問題。最後藉由蒙地卡羅分析法，在30%的電晶體通道寬度變動與繞線長度的變化下，我們的方法仍能保有平均2%的誤差。以及當我們在預估穿矽連接孔的電容時，我們的不準確度在8%以內。

關鍵字

穿矽連接孔；三維晶片；環型震盪器；敏感度分析

並列摘要

In this thesis, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation ring test, in which two TSVs are connected with some peripheral circuits to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring - a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. In addition to two TSVs to be characterized, we also present lots of TSVs characterization scheme to avoid the synchronous issue. Monte-Carlo analysis of a typical TSV with 30% width variation of transistors and routing wires variation occurring shows that characterization error of this method is average within 2% and the prediction of the capacitances of TSVs within 8%.

並列關鍵字

Through Silicon Via ； 3D IC ； oscillation ring ； sensitivity analysis

參考文獻

[1]. I. U. Abhulimen, A. Kamto, Y. Liu, S. L. Burkett, and L. Schaper, “Fabrication and Testing of Through-Silicon Vias Used in Three-Dimensional Integration,” Journal of Vacuum Science & Technology B, vol. 26, issue 6, pp. 1834-1840, Nov. 2008.

[2]. K. Arabi, H. Ihs, C. Dufaza and B. Kaminska, “Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits,” in Proc. of International Test Conference, pp. 91-100, 1998.

[3]. A. Bassi, A. Veggetti, L. Croce, and A. Bogliolo, “Measuring the Effects of Process Variations on Circuit Performance by Means of Digitally Controllable Ring Oscillators,” in Proc. of Microelectronic Test Structures, pp. 214-217, March 2003.

[4]. P. Y. Chen, C. W. Wu, and D. M. Kwai, “On-Chip TSV Testing for 3D IC Before Bonding Using Sense Amplification,” in Proc. of IEEE Asian Test Symposium, pp. 450-455, Nov. 2009.

[6]. B. P. Das, B Amrutur, H.S. Jamadagni, N.V. Arvind, and V. Visvanathan, “Within-Die Gate Delay Variability Measurement Using Re-Configurable Ring Oscillator,” in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp.133-136, Sep. 2008.

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應用敏感度分析於三維晶片內穿矽連接孔之特性研究

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