利用直接沉積高介電閘極氧化物於鍺半導體製作高效能金氧半元件

High Performance Germanium MOS Devices with Directly Deposited High-k Gate Dielectrics

朱龍琨

指導教授 ： 洪銘輝 ； 黃倉秀

國立清華大學/工學院/材料科學工程學系/博士(2012年)

https://doi.org/10.6843/NTHU.2012.00663

摘要

為了因應16奈米互補式金氧半技術的需要，在既有的矽半導體外，鍺半導體因為具有較高的載子遷移率而成為很有潛力的材料。高性能鍺金氧半元件必須同時達到極佳的高介電氧化物與鍺間的界面以及很低的等效氧化物厚度，然而因鍺本身有著不好的原生氧化物，使得要達成極佳的高介電氧化物與鍺間的界面變得十分困難。此研究利用在超高真空下直接沉積高介電氧化物於鍺上來製作金氧半元件，在沒有顯著的鍺擴散與界面層形成的情況下，達到氧化物的高介電常數與絕佳的氧化物與鍺間的界面。
在此論文中，分子束磊晶成長的氧化釔與氧化鎵(氧化钆)應用在鍺金氧半元件的製作。各樣的分析，包括化學、結構與電性都進行以了解此閘極層與界面。經由適當的退火與氟處理後，此鍺金氧半元件展現極高的特性，像是絕佳的電容-電壓特徵、低界面缺陷密度(1011 cm-2eV-1)、低漏電(小10-8 A/cm2)與高氧化鎵(氧化钆)界電常數(14到16)，這些都說明了此氧化物與界面的高品質與高熱穩定性。
進一步地，在金氧半場效電晶體中(線寬約1μm，等效氧化物厚度3.8 nm)，飽和電流密度、最高電導值與電洞遷移率分別高達496 μA/μm、178 μS/μm、389 cm2/V-s。當再降低氧化物厚度後，等效氧化物厚度則更小至約1.38 nm，伴隨著有系統的電晶體性能增益，使得飽和電流密度與最高電導值分別更達到約800 μA/μm與423 μS/μm，而電洞遷移率仍維持約300 cm2/V-s。氧化鎵(氧化钆)極佳的可微縮性以及其對於鍺表面鈍化的能力，使其具有相當的潛力在下世代鍺通道金氧半元件上被應用。

關鍵字

鍺 ； 金氧半元件 ； 高介電氧化物

並列摘要

When channel materials other than Si are urgently demanded to enhance the performance of complementary metal-oxide-semiconductor (CMOS) beyond 16 nm technology node, Ge has always been considered as one viable contender because of its mobility advantages compared to Si. A high-quality interface between high- dielectrics and Ge as well as a small equivalent oxide thickness (EOT) are necessarily required for future high-performance Ge MOS device. However, it is challenging to achieve a good oxide/Ge interface mainly due to the unfavorable surface properties and native oxides of Ge. This work approaches Ge MOS devices with direct deposition of high-κ dielectrics on Ge under ultra-high-vacuum (UHV), while a high κ value of the gate oxides and a decent oxide/Ge interface quality are maintained without significant Ge inter-diffusion and formation of interfacial layers (ILs).
In this dissertation, molecular beam deposited (MBD) high- Y2O¬3 and Ga2O3(Gd2O3) [GGO] have been utilized as the gate dielectrics for Ge MOS devices without using ILs. Comprehensive investigations have been carried out chemically, structurally, and electronically, to study the gate stacks, especially the oxide/Ge interfaces. With appropriate post oxide deposition treatment for the gate stacks with GGO, such as annealing and fluorine incorporation, the Ge MOS devices, i.e., MOS capacitors (MOSCAPs) and MOS field-effect-transistors (MOSFETs), have exhibited very high performance. Excellent capacitance-voltage (C-V) characteristics, a low interfacial density of states (Dit’s) in the range of 1011 cm-2eV-1, and a low gate leakage of less than 10-8 A/cm2 along with a high  value (14-16) of the GGO indicate the gate dielectrics and GGO/Ge interface are of high quality and thermally stable. Furthermore, the MOSFETs, with a gate length (Lg) of 1 μm an EOT of ~3.8 nm, have yielded high performance in terms of a high drain current density (Id), a maximum transconductance (gm), and hole mobility (μh) of 496 μA/μm, 178 μS/μm, and 389 cm2/V-s, respectively. When further reducing the oxide thickness, a smaller EOT of ~1.38 nm has been achieved. The device performance has been systematically enhanced in good agreement with the increased oxide capacitance, showing an Id of 800 μA/μm and a gm of 423 μS/μm in a MOSFET with a Lg of 1μm, while the μh remained ~300 cm2/V-s. The excellent GGO scalability and its effective passivation for Ge surface suggest GGO stands a good chance of realizing the applications of Ge-channel pMOS devices for next-generation CMOS technology.

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