低漏電差值感測基於PPN架構十電晶體組成次臨界電壓靜態隨機存取記憶胞

在這篇論文中，我們提出了一個由P-P-N反向器形成的差值感測十電晶體組成靜態隨機存取記憶胞能提供低功耗操作的功能。因為記憶胞穩定度在門檻電壓時特別容易受到雜訊影響，我們的記憶胞能避免讀取干擾使得記憶胞穩定度被大幅改善。此外，在沒有記憶胞穩定度的限制下，我們引入逆短通道效應來加強存取門戶電晶體以確保記憶胞寫入度。隨著奈米製程下電晶體漏電流現象變得越來越顯著，我們提出一套VGND偏壓模式以降低跟資料相關的漏電流影響。無需複雜的字元線控制，提出的記憶胞允許複數字元在一條字元線上以增加記憶胞密度並且允許有效率的使用錯誤更正碼。為了驗證提出的記憶胞，我們實作了一個含有16Kb提出的記憶胞的陣列使用90奈米製程。為了比較的考量，我們也實作了一個含有2Kb以前提出的記憶胞的陣列在晶片中。提供給陣列和周邊電路的電壓源被分開以支援周邊電路電壓調升和量測記憶胞陣列所消耗的漏電流。提高週邊電路電壓不只可以加快晶片操作速度，也可以解除操作在低電壓的限制，記憶胞陣列仍可操作在低電壓，大幅降低消耗的漏電流功率。晶片量測結果顯示16Kb提出的記憶胞陣列最低可以操作在285mV。藉由調升周邊電路電壓至400mV，提出的記憶胞陣列最低可以操作在265mV而且可以操作在更高的頻率。在300mV電壓源下，整個16Kb陣列消耗2.6uW。經過正規化後，提出的記憶胞只消耗了之前的記憶胞0.2倍的漏電流。

關鍵字

靜態隨機存取記憶體；低漏電；雜訊間隙；字元線漏電

並列摘要

In this thesis, we propose a P-P-N inverter based differential 10T SRAM cell capable of providing low power operation. Since cell stability is especially vulnerable to noise at sub-threshold voltage, the proposed cell avoids read disturb, improving cell stability significantly. Without cell stability concern, we strengthen the access transistors to ensure cell writability by employing reverse short channel effect. As transistor leakage becomes more prominent in nanometer technology, we introduce VGND biasing scheme to reduce the impact of data-dependent leakage current. Without complicate wordline control, the proposed cell allows multi-word on a wordline to increase cell density and to enable efficient error correction code (ECC). To verify the proposed cell, a 16Kb array of the proposed cell is fabricated in 90nm CMOS technology. For comparison, we also fabricate 2Kb array of previous work in our chip. Supply voltage for array and peripheral is separated to enable periphery voltage boosting and to measure the cell array leakage. Applying higher peripheral voltage not only enhances the chip operating speed but also resolve the operating limitation at low voltage while the cell array still operates at lower voltage, reducing leakage power significantly. Measurement results show the 16Kb array of the proposed cell can work successfully down to 285mV. By boosting periphery voltage to 0.4V, the proposed cell can work at a lower (265mV) voltage and operate at a higher frequency. The entire 16Kb array consumes 2.6uW leakage power at 300mV. After normalization, our cell consumes only 0.2X leakage current compared to previous work.

並列關鍵字

SRAM ； Low leakage ； Noise margin ； Bitline leakage

參考文獻

[1] B. Calhoun and A. Chandrakasan, “Static noise margin variation for sub-threshold SRAM in 65 n-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, pp. 1673–1679, 2006.

[3] T. Kim, J. Liu, J. Keane, and C. Kim, “A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 518–529, Feb. 2008.

[4] B. Zhai, D. Blaaauw, and D. Sylvester, “A variation-tolerant sub-200 mV 6-T subthreshold SRAM,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2338–2348, Oct. 2008.

[5] N. Verma and A. Chandrakasan, “A 256 kb 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Jan. 2008.

[6] T. Kim, J. Liu, and C. Kim, “A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785–1795, Jun. 2009.

國際替代計量

低漏電差值感測基於PPN架構十電晶體組成次臨界電壓靜態隨機存取記憶胞

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