High-level Transition Fault Simulator and its Applications on Functional Diagnosis for JPEG Decoder

適用於診斷JPEG解碼器晶片之高階轉態延遲錯誤模擬器

簡佐樺(Tso-Hua Chien)

指導教授 ： 劉靖家

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

https://doi.org/10.6843/NTHU.2010.00700

摘要

Continuous shrinking process technology enables us to implement a parallel software system
on a chip multiprocessor (CMP). However, defects on such a large number of cores lead to low
system yield. For high system yield, it is important to model defects in functional mode. By understanding
the defective behavior, we can further diagnose the system problems, and even fix them
with reconfiguration of software. In this thesis, we propose a software transition fault simulator
for chip multi-processors with application on functional diagnosis for JPEG decoder. Firstly, we
introduce a software transition fault model and fault simulator to efficiently obtain the functional
behaviors of structural delay defects for CMP applications without the overheads of executing processor
models. Then we implement a ISS-based transition fault simulator to verify correctness of
software transition fault simulator. If application has array elements, there are some mismatchs
between software and ISS-based, so we build a extended model to match difference. Then, a feature
selection tool is used to dump the features of fault simulation results and rank these features
according to their ability to represent a particular set of defects. By constructing a fault dictionary
that maps structural defects to functional features of CMP application, we can diagnose the faulty
processor components in a defective CMP. In experiments, we demonstrate the above concept on a
JPEG decoder implemented in a CMP. Comparing the result of software and ISS-based, software
transtion fault have 90 times speedup in performance and still have high correctness. The diagnosis
results show that the feature selection procedure can exactly map structural defects to different
functional behaviors.

關鍵字

轉態延遲錯誤 ； 模擬器 ； 診斷

並列摘要

隨著製程演進，讓我們可以在多核心處理器晶片上設計出平行程式系統。但因晶片面積增加，缺陷會讓整體系統良率下降，所以建立功能型式的缺陷模組顯得更加的重要。我們可以透過了解缺陷的錯誤行為，進一步診斷系統錯誤的位置，甚至使用可重組態軟體去修正這些系統錯誤。在這篇論文中，我們提出一個適用於診斷JPEG解碼多核心處理器晶片之轉態延遲錯誤模擬器，此方法能提高多核心處理器晶片的可靠度。首先，我們建立軟體轉態延遲錯誤模組及模擬器，可以有效模擬硬體結構延遲錯誤對多核心處理器晶片應用程式錯誤的影響，而且因為晶片中沒有加入處理器模組，所以沒有額外的執行時間負擔，進而快速產生模擬結果。並且我們實作出指令集轉態延遲模擬器，此模擬器用來驗證軟體轉態延遲模擬器的正確性。當應用程式需要存讀矩陣時，軟體模擬器會出現誤差，故根據矩陣的資訊，我們建立了一個延伸模組來修正這些誤差。模擬器的目的在於提供資訊用於診斷出多核心處理器晶片上的哪一個處理器中存在轉態延遲缺陷，並且能夠診斷出該處理器的何種算術運算受到轉態延遲缺陷的影響，所以我們利用特性選擇軟體，從軟體轉態延遲錯誤模擬器的模擬結果中，找出模擬錯誤行為結果的特性，並且根據特性的重要程度排名，藉此描繪缺陷的特性組合。透過建立錯誤字典，將結構缺陷對映到多核心處理器晶片應用程式的功能特性，我們可以診斷出有缺陷的多核心處理器晶片中，缺陷存在於哪一個元件。在實驗中，軟體轉態延遲錯誤模擬器比指令集模擬器快了300倍以上，即使加上延伸模組速度也提升了70倍以上。診斷結果也顯示了可以有效地將結構上的缺陷對映不同的功能行為特性。

並列關鍵字

Transition fault simulator ； JPEG decoder ； Functional diagnosis

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