考慮電壓降之零時序差異時脈樹研究

Zero Skew Clock Tree Considering Voltage Drop Effect

劉奕章(Yi-Chang Liu)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2005年)

https://doi.org/10.6840/cycu200500089

摘要

時脈樹一直為影響電路效能和功率消耗的主要因素，現今電路的設計有趨向於低功率的需求，因此隨著供應電壓及元件尺寸的減小，電壓降(Voltage Drop)的影響也變的愈來愈重要。一個循序電路的速度，依據電路的critical path delay。但一個循序電路的功能是否正常，時脈樹的時脈訊號是否同時到達每個暫存器(flip-flop)是主要的因素。在深次微米的技術下，5%的電壓降會造成15%的元件時序延遲增加[1]。所以當晶片上分佈著不同的電壓降時，若不考慮電壓降所造成的時序延遲的效應，則所設計的晶片會有時序的問題。因此如何在考慮電壓降的影響下，建造出零時序差異的時脈樹(zero skew clock tree，簡稱ZST)，則成為現今一個重要的課題。
本篇論文提出一個以DME為基礎的時脈樹產生器(clock tree generator)。我們提出的演算法是在建置時脈樹時，考慮因電壓降造成clock buffer時序延遲的改變。首先在建置時脈樹之前，先計算出此時晶片上的電壓降分佈，在根據這個電壓降分佈，用DME的演算法建置零時序初始時脈樹。由於在建置初始時脈樹時要插入clock buffer，所加入的clock buffer也會影響電壓降的值，因此在建置完時脈樹後，會造成電壓降分佈的改變，而產生時序差異。使得初始時脈樹變成非零時序差異，所以最後我們再調整時脈樹的線長，來完成我們零時序差異時脈樹的目標。
由實驗可以發現，在建置初始時脈樹就考慮電壓降，將可以得到較佳的時脈樹成本。當建置時脈樹時，時脈樹成本只針對latency或wire length作改善，得到的結果平均分別改善了11.38%和8.98%。詳細的實驗請參考第五章。

關鍵字

電壓降 ； 零時序差異時脈樹

並列摘要

The clock tree has been the main factor of the performance and power consumption of a circuit. Recent designs tend to have low power consumption requirement. As the reducing of power supply voltage and the decreasing size of the devices, the impact of the voltage drop becomes more and more important. The frequency of a sequential circuit depends on the delay of the critical path. The main factor for the sequential circuit to work correctly should rely upon the simultaneous arrival of the clock signal at each register. In the deep submicron technology, five-percentage of voltage drop will increase fifteen-percentage of gate delay [1]. So if a designer does not consider the effect of gate delay caused by the voltage drop, which are distributed on the chip, the chip will have timing problem. Therefore, how to build a zero skew clock tree under the effect of voltage drop is becoming an important issue.

This paper proposed a clock tree generator base on Deferred-Merge Embedding (DME) method. The proposed algorithm will consider the increase of clock buffer delay due to the voltage drop during the clock tree synthesis. Before building the clock tree, we first calculate the distribution of voltage drop on the chip, then an initial zero skew clock tree will be built according to the distribution of the voltage drop and DME algorithm. During the process of building the initial clock tree, buffers are inserted. These inserted clock buffers will also affect the value of voltage drop. So after building the initial clock tree, the distribution of voltage drop on the chip is changed, that causes the clock skew. Finally we adjust the wire length of the clock tree, to adjust the clock skew such that to reach the goal of zero skew clock tree.

The experimental results show that, when build clock tree include voltage drop effect can obtain a better clock tree cost. The clock tree cost only consider latency or wire length at building clock tree, the average performance improves 11.38% and 8.98% finally. Detailed experimental are shown in chapter 5.

並列關鍵字

voltage drop ； zero skew clock tree

參考文獻

[6] S. Hussain, S. Rochel, D. Overhauser, and R. Saleh, "Clock Verification in the Presence of IR-Drop in the Power Distribution Network," in Proc. IEEE Custom Integrated Circuits Conference, pp. 437-440, May 1999

[7] J-S. Yim, S-O. Bae, and C-M. Kyung, “A floorplan-based planning methodology for power and clock distribution in ASICs,” in Proc. 36th ACM/IEEE Design Automation Conference, pp. 766-771, June 21-25, 1999

[8] G. Steele, D. Overhauser, S. Rochel, and S. Z. Hussain, “Full-chip verification methods for DSM power distribution systems,” in Proc. 35th ACM/IEEE Design Automation Conference, pp. 744-749,1998

[9] A. Dharchoudhury, R. Panda, D. Blaauw, and R. Vaidyanathan, “Design and Analysis of Power Distribution Networks in PowerPCTM- Microprocessors,” in Proc. 35th ACM/IEEE Design Automation Conference, pp. 738-743, 1998

[1] D-S. Cho, K-H. Lee, G-J. Jang, T-S. Kim, and J-T. Kong, ”Efficient Modeling Techniques for IR drop Analysis in ASIC Designs,” in Proc. IEEE ASIC/SOC Conference, pp. 64-68, 1999