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  • 學位論文

加速三維積體電路及電子系統層級設計開發之方法研究

Design Methodologies for Speeding up the Development of 3D ICs and Electronic System-Level Designs

指導教授 : 黃世旭

摘要


因應晶片設計的複雜度提升,運用三維積體電路進行系統整合,並以電子系統層級進行高階設計及虛擬平台分析,已成為目前晶片設計的趨勢。因此此設計趨勢,在本篇論文中,我們提出兩個加速早期開發的方法:(1)在三維積體電路階層分派階段,我們提出降低溫度上升的最佳化及啟發式演算法;(2) 對於電子系統層級設計,提出自動將系統層次模型轉換到真實的匯流排傳輸方式之方法。 在三維積體電路中,由於在不同階層之間的熱導率很低,因此降低電路溫度的上升是必須的。在本篇論文中,我們證明在三維積體電路的設計下,不同的階層分派結果會導致不同的溫度上升。基於這個原因,我們在考慮熱效應下進行階層分派。我們的研究成果主要包括兩部分。首先,使用混合整數線性規劃的方法,能保證了最小化的溫度增加。其次,提出了複雜度為多項式時間下的啟發式演算法來降低溫度上升。實驗結果顯示,我們的整數線性規劃方法和啟發式算法都能有效降低溫度,且僅增加少量的晶片面積。 在電子系統層級中,現有的設計流程中缺乏有效的設計方法將系統層次TLM 2.0 模型傳輸轉換到真實的匯流排 AXI 傳輸方式。因此,在使用 TLM 2.0模型傳輸模擬驗證後,設計者需要花費大量的人力,將 TLM 2.0 模型傳輸的傳輸機制,轉換成真實的匯流排 AXI傳輸方式。有鑑於此,我們提出了將抽象匯流排界面單元自動化的概念。主要的想法為在匯流排界面單元中提供內建函數的功能,且提供其能與TLM2.0及真實匯流排AXI的溝通機制。結果顯示,設計者只需使用我們提供的函數便能與匯流排溝通,不需要考慮匯流排界面單元的實現細節。

並列摘要


As the design complexity continues to increase, three-dimensional integrated circuits (3D IC) and electronic system-level (ESL) design have become two design trends. For the two design trends, in this dissertation, we propose two design methodologies to speed up the development of 3D ICs and ESL designs. First, in the 3D IC design, we propose a temperature-aware layer assignment to effectively reduce the temperature increase at the early design stage, Second, in the ESL design, we propose an automatic approach to transform transaction level modeling (TLM) communications to the real bus protocol (the AXI bus protocol) In the 3D IC, due to the low thermal conductivities of dielectrics between active layers, there is a need to reduce the temperature increase of three-dimensional integrated circuits (3D ICs). We demonstrate that, in the design of 3D ICs, different layer assignment results often lead to different temperature increases. Based on this observation, we are motivated to perform temperature-aware layer assignment. Our work includes two parts. Firstly, an mixed integer linear programming (MILP) approach that guarantees a minimum temperature increase is proposed. Secondly, a polynomial-time heuristic algorithm that reduces the temperature increase is proposed. Experimental results show that both our MILP approach and our heuristic algorithm produce a significant reduction in the temperature increase with a very small area overhead. On the other hand, the existing ESL design flow lacks of an effective design methodology to transform TLM communications to the real bus protocol (the AXI bus protocol). Therefore, after the design is verified through TLM 2.0 simulation, the designers need to spend a lot of efforts to transform TLM 2.0 communication mechanisms to the real bus protocol. Based on this observation, we propose the concept of abstract bus interface unit (BIU) for automatic transformation. The main idea of our BIU is to provide built-in functions that realize TLM 2.0 communication mechanisms and the AXI bus protocol, respectively. As a result, the designers only need to use our provided function calls to perform communications and do not need to worry about the implementation details.

參考文獻


[18] Lih-Yih Chiou; Liang-Ying Lu; Zhao-Hong Chen; Yu-Hsiung Su; Jen-Chieh Yeh; Yi-Fan Chen; Shih-Che Lin, "System thermal analysis of 3D IC on ESL virtual platform," SoC Design Conference (ISOCC), 2013 International , pp.394,397, 17-19 Nov. 2013
[15] I-Yao Chuang; Chi-Wen Chang; Tso-Yi Fan; Jen-Chieh Yeh; Kung-Ming Ji; Jui-Liang Ma; An-Yeu Wu; Shih-Yin Lin, "PAC Duo SoC performance analysis with ESL design methodology," ASIC, 2009. ASICON '09. IEEE 8th International Conference on , pp.399,402, 20-23 Oct. 2009
[31] Thomas H. Cormen; Charles E. Leiserson; Ronald L. Rivest; Clifford Stein, "Introduction to Algorithms" (third edition), MIT Press, 2009.
[3] Jian-Qiang Lu, "3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems," Proceedings of the IEEE , vol.97, no.1, pp.18,30, Jan. 2009
[4] V.F. Pavlidis and E.G. Friedman, "Three-Dimensional Integrated Circuit Design", Morgan Kaufmann Publishers, 2009.

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