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  • 學位論文

三維晶片之內埋式中介層基板平坦化研究

Flatness Investigation of the Embedded Interposer of 3D-ICs

指導教授 : 李昌駿

摘要


近年來,隨著科技進步與創新,大眾要求也隨之提高,使電子封裝趨向輕薄、高效能、高密度分佈、多功能與高耐久度等方向發展,一般而言,半導體元件微小化可依靠微影技術,然而現今微影技術已接近並達到其物理極限,為解決微影技術之限制,封裝型式從平面發展演變成三維堆疊,形成今日之三維積體電路(3D integrated circuits, 3D-ICs)並成為現今主要趨勢。此外,三維積體電路由各類關鍵晶片模組組裝而成,在產品設計方面,除了針對其單一晶片組件之效能,亦須考量個元件之異質整合之整體效能的表現。 電子元件透過內埋式中介層載板(Embedded Interposer Carrier, EIC)連接基板與晶片之電訊號,而內埋式中介層於製造過程中,異質材料薄膜堆疊過程所引起之嚴重翹曲為待已解決之問題,於是本研究提出一環型框架獨特設計引入內埋式中介層載板進行組裝製造,並通過有限元素法與全因子設計法之結合,選出最低翹曲量之多層堆疊薄膜,鋼板環形框架與內埋式玻璃中介層載板組裝所產生之翹曲量經有限元素法模擬估算為169μm,分析結果顯示環型框架具有較高之彈性模數,可有效抑制內埋式中介層載板因製程產生之翹曲量。通過本研究之內埋式中介層載板平坦化研究,有望提升3D-ICs組裝可靠度。

並列摘要


With the advancements in technology, electronics products are continuously being miniaturized, low weight and multi-functions in recent years. Generally, lithography procedures are used in the semiconductor industry to achieve the desired miniaturization but are bound by physical limits which are hard to overcome. To resolve this problem, planar 2D integration is proposed to be replaced by 3D stacking. 3D integrated circuits (3D-ICs) is expected to be more mainstream in the following years. In addition, 3D-ICs is assembled from different types of chips. The performance in the integration of different materials must be considered in product design. To resolve and simplify the critical assembly issue regarding the interposer of 3D integrated circuits, a prototype of an embedded interposer carrier (EIC) is developed and show in this research. To complete good co-planarity of the EIC assembled by either dies or a printed circuit board, serious warpage induced during the laminating process of multi-stacked organic films needs to be resolved. Hence, a unique design with an additional ring-type stiff frame is proposed and introduced into EIC fabrication. Through process-based simulation combined with the full factor design approach, a restraint for the warping of EIC lower than 169 μm is estimated; a steel-made ring-type frame combined with suitable conjugations of laminated materials is considered. Consequently, the assembly reliability of 3D-ICs through EIC technology is expected to increase significantly.

參考文獻


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