第四族半導體合金於二維/三維奈米級鍺基金氧半導體元件之應變工程分析與研究

為了提升先進半導體元件的操作特性，相關技術之趨勢隨著年份發展除了持續對通道長度進行微縮、金屬閘極/高介電係數氧化層製程以及採用高遷移率的通道材料，包含:鍺、矽鍺和三五族材料，同時導入源/汲極(S/D)晶格不匹配引致應力源和沉積時內含高內應力之接觸蝕刻停止層薄膜(Contact Etch Stop Liner, CESL)，綜合上述各方法來延續莫爾定律之準則。另一方面，當技術節點由20奈米發展至16/14奈米之鰭式電晶體時，元件亦由二維平面式朝向三維之鰭式電晶體方向發展，前述之三維鰭式電晶體結構有別於傳統之平面電晶體，且基於製程的複雜化和材料應用之複雜程度，因此釐清鰭式電晶體中各組件之沉積和磊晶製程對其機械性質之影響，同時考慮並分析後閘極製程(Gate-Last Process)之力學響應，為分析應變工程對鰭式電晶體之效益之關鍵議題。綜上所述，本研究著重於比傳統矽基材有更優異遷移率之鍺基元件分析，針對短通道之平面式電晶體以及鰭式電晶體之佈局樣式影響和元件增益幅度進行分析，以尋求圖案化結構設計上之優化和複數應力源之影響幅度探討。分析結果指出當鍺基之NMOSFET於源/汲極鑲埋Ge0.86Si0.14合金並額外沉積一含+1 GPa拉伸應力之CESL層時，其最大載子遷移率增益為55.14%。具源/汲極鑲埋Ge0.93Si0.07合金、延伸閘極和啞作動區之鍺基NMOSFET，其最大載子遷移率增益為31.40%。另一方面，具源/汲極鑲埋鍺錫合金、延伸閘極和啞作動區之鍺基PMOSFET沉積一含-1 GPa壓縮應力CESL層，其最大載子遷移率增益為81.99。而對三維鰭式電晶體之佈局樣式設計來說，則建議採用較長之源/汲極區域長度和較短之通道長度以增進元件通道方向之應力值。

關鍵字

鍺基元件；應變工程；有限元素分析；晶格不匹配應力；接觸蝕刻停止層

並列摘要

Currently, strain-engineering techniques are well established in Si-based metal–oxide semiconductor ﬁeld-effect transistor (MOSFET)technology. To compensate for the drawback of device-size reduc-tion, germanium-substituted silicon is chosen as a channel material.Ge exhibits highly enhanced carrier mobility and it is regarded to be apromising channel material in a nano-scale MOSFET beyond the sub-22 nm technology node. This element has attracted considerable at-tention because of its potential to enhance the drive current of MOSFETsby replacing traditional strained Si-channel technology. Implanting Siatoms in the source/drain (S/D) region on the Ge substrate is a con-ventional method. Si and Ge atoms generate lattice mismatching,which improves device efﬁciency. Thus, this study adjusts the layout pattern of the device and usea 3D ﬁnite element model to simulate channel stress and mobility. Bycombining appropriate S/D stressors composed of Ge1 − x Six alloyswith the CESL at the considered intrinsic stress points, a signiﬁcant en-hancement in the performance of tensile strained Ge-based nMOSFET can be acquired. Moreover, the strained GeSn alloy embedded into a Ge-based device is considered as a promising solution of next generation advanced devices. In contrast with Si, Ge, C in group IV semiconductor devices, GeSn alloy is indeed a novel material adopted in strained engineering. On the other hand, the arrangement of device layout also plays an important rule to influence device performance as S/D stressors are exerted. However, the analysis regarding comprehensive effects integrated GeSn stressors with the layout of that salient gate width extends across a dummy active diffused region (Dummy OD) is little. For this reason, a reliable device stress simulation is proposed and performed to explore the above-mentioned concerns under the vehicle consideration of a 20 nm Ge-based pMOSFET with a 100 nm gate width and a 100 nm dummy gate width. For the FinFETs layout design, the larger S/D region length and narrow channel length was suggested to enhance the longtidual stress of concerned channel.

並列關鍵字

Ge-based Devices ； Strain Engineering ； Finite Element Analysis (FEA) ； Lattice Mismatch Stress ； Contact Etch Stop Liner (CESL)

參考文獻

[1] S. E. Thompson et al., “A 90-nm logic technology featuring Strained-Silicon,” IEEE Trans. Electron Devices., vol. 51, no. 11, pp. 1790-1797, Nov. 2004.

[2] G. Eneman et al., “Gate influence on the layout sensitivity of Si1−xGex S/D and Si1−yCy S/D transistors including an analytical model,” IEEE Trans. Electron Devices., vol. 55, no. 10, pp. 2703-2711, Oct. 2008.

[3] D. Zhang et al., “Embedded SiGe S/D PMOS on Thin Body SOI Substrate with Drive Current Enhancement,” in Proc. VLSI Symp. Tech. Dig., 2005, pp. 26–27.

[4] W. S. Liao et al., “PMOS hole mobility enhancement through SiGe conductive channel and highly compressive ILD-SiNx stressing layer,” IEEE Electron Device Lett., vol. 29, no. 1, pp. 86-88, Jan. 2008.

[5] Y. C. Liu et al., “Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy,” in Proc.VLSI Symp. Tech. Dig., 2007, pp. 44–45.

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第四族半導體合金於二維/三維奈米級鍺基金氧半導體元件之應變工程分析與研究

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