以0.18μm製程實現壓控振盪器與鎖相迴路

An Implementation of VCO & PLL by 0.18μm process

張煌輝(Huang-Hui Chang)

指導教授 ： 蔡澈雄

崑山科技大學/工程學院/電子工程研究所/碩士(2012年)

摘要

本論文中將四級差動環形壓控振盪器(VCO)應用於鎖相迴路(PLL)之中，而本文中所模擬的四級環形壓控振盪器具有好的寬調頻範圍及低相位雜訊，模擬顯示出此振盪器能穩定於0.9V到1.8V電壓工作，電壓穩定在1.8V時的振盪頻率為2.272GHz，而電壓在0.9V時的振盪頻率為3.372GHz，我們將這振盪器與相位頻率偵測器、充電泵、低通濾波器、除頻器作結合，進行整個鎖相迴路的模擬與驗證。實驗中我們利用H-Spice進行電路的模擬測試，壓控振盪器與鎖相迴路相關元件之製程為TSMC 0.18μm。
模擬方面，我們利用H-Spice來做模擬，壓控振盪器有頻寬調變範圍，控制電壓由0.9V到1.8V，振盪頻率從2.272GHz到3.372GHz，PLL鎖定頻率大約在50MHz，最後模擬出來進行Layout的繪製，PLL的低通濾波器包含在晶片中，電容方面，使用PMOS、NMOS分別製作，晶片面積為371.35x362.95μm2。

關鍵字

壓控振盪器 ； 鎖相迴路

並列摘要

In this thesis, the VHF and UHF bands oscillator which mainly composed of four cascaded differential double delay ring oscillator. The VCO (Voltage-Controlled Oscillator) is also applied on PLL. The VCO with high tuning range, and low phase noise, Their output frequency will be 3372 MHz, 2272 MHz under 0.9 volts and 1.8 volts respectively. We integrate voltage controlled oscillator and phase frequency detector, charge pump, low-pass filter, and frequency divider to implement a PLL (Phase-Locked Loop) circuit. The VCO circuits are simulated and verified by H-Spice, with tsmc 0.18μm technology. For PLL circuit is simulated by H-Spice only.
In the simulated PLL circuit, voltage controlled oscillator has high tuning range, control voltage with 0.9V to 1.8V. The tuning frequency is from 2272MHz to 3372MHz. The PLL locked frequency is 50MHz. We had implemented PLL IC layout and executed post layout simulation. For Low-Pass Filter included in PLL, the capacitor is created in PMOS and NMOS type respectively. The complete PLL including it’s on-chip loop filter occupies 371.35x362.95μm2 chip area.

並列關鍵字

PLL ； VCO

參考文獻

[16] 張家祥，”以主動負載差動放大器為基礎的壓控振盪器與鎖相迴路之研究”， 崑山科技大學電子工程研究所碩士論文，中華民國九十九年六月。

[14] 林明信，”以差動放大器為基礎的壓控振盪器與鎖相迴路之研究”，崑山科技大學電子工程研究所碩士論文，中華民國九十六年六月。

[15] 陳家弘，”以差動放大器和NDR環形壓控振盪器為設計基礎之鎖相迴路”，崑山科技大學電子工程研究所碩士論文，中華民國九十五年六月。

[4] J. Craninckx and M. Steyaert, “A 1.8-GHz low-phase noiseCMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, May 1997, pp. 736–744.

[5] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6-μm CMOS,” IEEE J. Solid-State Circuits, vol. 34, May 1999, pp. 586–591.