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  • 學位論文

ASIC 實體設計自動化系統 -- 品質管控,流程改善及完工預測 以 A 公司為例

Quality Assurance, Flow Improvement and Tapeout Prediction Automation System of ASIC Physical Design

指導教授 : 鍾惠民 劉助
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摘要


摘要 ASIC 實體設計,將RTL/Gate Level經由設計轉換成晶圓廠可以生產的光罩藍圖 (GDS) ,其所花費的時間占整體IC設計約百分之四十,同時流程中使用的EDA 軟體也近20種,建置成本高達上億新台幣,再加上昂貴的光罩費用(先進製程動則上億新台幣,7奈米,10-15M USD),零錯誤成為必須。因此如何確保實體設計的品質,並縮短設計流程 (Time to Market) 成為所有ASIC設計公司 (特別是 ASIC 設計服務公司) 努力的目標。 本研究所建立的自動化系統,預期能取代傳統人工方式的品質驗證與流程的串接 (提升效率),同時藉由資料的收集,讓系統達到可以自行判斷品質 (提升品質),找出流程中最耗時最需要改善的步驟 (流程改善),提供所有專案即時進度監控並能預測專案完成時間 (進度與完工預測)。 此外,在成本的節省和接案的數量上亦將有可觀的進步,預估新人訓練成本將可節省約60%,專案的人事費用將節省近45%,同時接案的數量也可以增加約1.4倍。除了這些有形的成本外,另外在人事異動時的項目交接,人為疏失而導致的重做,等專案執行相關無形成本上也會有很大的幫助。 簡單來說這將是一套幫助公司將無形的專案執行所需的紀律,細節,品質轉換成有形的可以依循的自動化系統。並能借由所收集的資料,讓系統,流程自我成長,不斷的進步。最終提高業務及設計部門的可擴展性(Scalable Business)。

並列摘要


Physical design automation system – It’s a system that built for ASIC Physical design including DFT (Design for Testability), Timing closure and APR (Automatic Place and Route) to ensure the quality of physical design and achieved first silicon success for every single project. ASIC designs in the deep sub-micron process (16/12/7/5 nm) are getting more and more complicated. Over 1000 Million logic gates design become mainstream in HPC (High-Performance Computing)/AI design. Along with the complicity, the wafer cost also reached 10 to 15 million USD in the 7nm/5nm process. Any single mistake will lead to entire project fail and millions loss of a company. Other than this, the stress of cost down from customer leads to the use of outsourcing engineers and low-cost engineers a must. The members of one project are normally across a few counties and locations. A standard SOP, including flow and quality check mechanism, is essential to project success. The Physical Design Automation System is built to overcome challenges list above. The system including flow tracer which contents all standard flow and pre-defined link of each step; QoR system, including automatic quality check after each stage; schedule management, provide a dynamic tapeout date prediction; The status dashboard system enables real-time status review and resource allocation. It’s a system that built with project execution discipline in each stage to achieve 100% quality check and ease the problems caused by outsourcing/low-cost manpower. It’s the foundation of ASIC design service company and also the foundation of a scalable business.

參考文獻


參考文獻
[1] Gartner. (2017). Market Share Analysis: Semiconductors, Worldwide, Preliminary 2017 Estimates. Retrieved from https://www.gartner.com/doc/3841764/market-share-analysis-semiconductors-worldwide
[2] insights, I. (2017). Fabless IC Company Sales Top $100 Billion for First Time Ever. Retrieved from http://www.icinsights.com/news/bulletins/Fabless-IC-Company-Sales-Top-100-Billion-For-First-Time-Ever/
[3] Prahalad, C. K., & Hamel, G. (2006). The core competence of the corporation. In Strategische unternehmungsplanung—strategische unternehmungsführung (pp. 275-292): Springer.
[4] TechNews. (2018). 2018 年第三季全球前十大 IC 設計公司營收排名出爐,僅高通微幅衰退. Retrieved from https://technews.tw/2018/11/21/q3-top10-ic-design-company-revenue-rankings/

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