適用於感知無線電異質網路下之空域-時域頻譜偵測演算法

Spatial-Temporal Spectrum Sensing in Cognitive Radio Heterogeneous Networks

李珮華(Pei-hua Lee)

指導教授 ： 蔡佩芸

國立中央大學/資訊電機學院/電機工程學系/碩士(2014年)

摘要

本論文提出了用於感知無線電異質網路下之空域-時域頻譜偵測演算法：感知無線電用戶(cognitive radio user)，又稱為次要使用者，在感知無線電異質網路(cognitive radio heterogeneous network)中，透過與鄰居合作以交換彼此的資訊，藉由對主要使用者傳送端的定位，判斷次要使用者位於主要使用者的傳送能量涵蓋範圍之內或之外，來區分合作對象，並利用分散式合作頻譜能量偵測，偵測出不影響主要使用者情況下的頻段，以供次要使用者傳送資料。其中對主要使用者傳送端定位的部分是結合插入權重演算法(Weighted Interpolation, WIP)來定位和馬可夫鏈(Markov Chain)的能量遞迴運算的定義，次要使用者只需與鄰居交換定位資訊，即可在有效的遞迴次數裡，定位出主要使用者傳送端位置。在本論文設定的環境下，相較於其他篇文獻，我們所提出的演算法在不同網路大小下，當網路空域-時域假警報機率(P_(f,net))為0.1時，網路空域-時域偵測機率(P_(d,net))都能有大於0.97的偵測效能。
我們除了使用演算法作感知無線電異質網路內所有次要使用者的效能模擬和比較外，也設計出單一次要使用者應用該演算法之硬體，其中遞迴的部分，我們使用資料回授的概念，以較多的時脈來節省硬體面積，在硬體設計上，利用簡化演算法或是共用硬體來減少硬體面積，並使用管線式(pipeline)來提升運算速度。次要使用者只需利用此硬體與鄰居交換資訊，即可找出空域或時域中閒置(idle)的頻帶來傳輸資料。最終的硬體設計以FPGA型號：Virtex6 XC6VLX550T來作驗證，其中操作頻率為47.536MHz，硬體運算單元總共使用了4顆乘法器、2顆CORDIC除法器、1顆CORDIC絕對值器，為一低硬體複雜度的設計。

關鍵字

感知無線電異質網路 ； 頻譜偵測演算法

並列摘要

In this paper, we propose an algorithm for spatial-temporal spectrum sensing in cognitive radio heterogeneous networks. In cognitive radio heterogeneous networks, cognitive radio users, also called secondary users, communicate with neighbors to share their information. In order to identify cooperative neighbors, each secondary user locates the position of the primary user. The weighted interpolation (WIP) algorithm is used to obtain the primary user’s position and then the secondary user know whether it is in the cell coverage or not. The distributed consensus algorithm is then used to combine the energy information gathered in each secondary user. With positioning and consensus combining algorithm, the proposed algorithm outperforms the conventional algorithm for spatial-temporal spectrum sensing in cognitive radio heterogeneous networks. When the network spatial-temporal false alarm probability, P_(f,net), is 0.1, the network spatial-temporal detection probability, P_(d,net), can be greater than 0.97.
The hardware for each cognitive radio secondary user is also designed and implemented. It consists of location, energy combination, and decision blocks. Hardware sharing technique is used to be simplified. Finally, we verify the design by FPGA, Virtex6 XC6VLX550T. The operation frequency is 47.536MHz. And the arithmetic units are four multipliers, two CORDIC dividers, and a CORDIC absoluter. The hardware is a low complexity design.

參考文獻

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