Translated Titles

Delay-locked Loop and It's Applications


陆平(Ping Lu);郑增钰(Zeng-Yu Zheng);任俊彦(Jun-Yan Ren)

Key Words

锁相环 ; 延迟锁定环 ; 鉴相器 ; 电荷泵 ; 压控延迟线 ; PLL ; DLL ; phase and frequency detector ; charge pump ; VCDL



Volume or Term/Year and Month of Publication

25卷1期(2005 / 02 / 25)

Page #

81 - 88

Content Language


Chinese Abstract


English Abstract

DLL may generate an accurate delay which is rarely affect ed by circumstance and process condition s, so it is used to generate stable delay or multi-phase clocks. The structure of DLL is introduced and the CMOS circuit of DLL is designed too. The new fake differential delay cell is emphasized because it can simplify the circuit and make it choose delay time more flexibly. The DLL applied to high-speed Ethernet transmitter is designed and simulated by Spice. DLL can control the rise and fall time of data transmitted within 4ns±1ns. The simulation is done with 0.35 micron standard CMOS process technology and 3.3V power supply.

Topic Category 基礎與應用科學 > 物理
工程學 > 電機工程