Compact Test Generation Using a Frozen Clock Testing Strategy

Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.

並列關鍵字

automatic test generation ； compact test sets ； frozen clock testing strategy ； sequential circuit testing ； test vector compaction

被引用紀錄

Moser, M. M. (2016). 1990 時代聯合國在薩爾瓦多之和平重建策略 [master's thesis, Tamkang University]. Airiti Library. https://doi.org/10.6846/TKU.2016.00509

趙威翔（2014）。青年參與環境議題對社會永續之影響〔碩士論文，淡江大學〕。華藝線上圖書館。https://doi.org/10.6846/TKU.2014.00692

詹小玫（2010）。探索成人女性學習的未來圖像〔碩士論文，淡江大學〕。華藝線上圖書館。https://doi.org/10.6846/TKU.2010.00818

陳隆政（2003）。可程式化神經肌肉穴位電刺激器〔碩士論文，中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu200300257

金惠卿（2001）。商店設計表現方式之空間印象研究--以Esprit, Levi's服飾旗鑑店為例〔碩士論文，中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu200100518

國際替代計量

Compact Test Generation Using a Frozen Clock Testing Strategy

全文下載

主題瀏覽