利用化學氣相沉積實現應變鍺錫n-型電晶體之高載子遷移率

High Electron Mobility in Strained GeSn n-MOSFETs by Chemical Vapor Deposition

莊嚴(Yen Chuang)

指導教授 ： 李峻霣

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2021年)

https://doi.org/10.6342/NTU202100367

摘要

擁有高遷移率的鍺錫材料很有潛力成為下一代邏輯元件的通道材料。當鍺錫薄膜受到鍺鬆弛緩衝層的壓縮應力時，其電洞載子遷移率將會被提升。另一方面，當鍺錫薄膜中錫比例超過8~11%，或是到受拉伸應變時，鍺錫薄膜將會變成直接能帶材料，此時電子會開始聚集在擁有較小等效質量的直接能帶中，使鍺錫材料電子遷移率提升。然而，目前對於鍺錫電子遷移率的研究仍偏少，要成長直接能帶的鍺錫薄膜，或是利用直接能帶鍺錫薄膜製作元件，都具有相當的難度。因此，本論文將針對鍺錫薄膜磊晶、薄膜熱穩定性、二極體元件、金屬/鍺錫接面到電晶體元件製程，進行完整的研究。
第一部分，我們在現有的化學氣相沉積系統中，估算鍺錫薄膜的成長條件與流量，加設了鍺與錫專用的前驅物氣體管線、發泡系統與氣櫃，並成長出高品質的鍺錫薄膜。同時我們利用改變成長條件或使用應變緩衝層，成長出高錫比例或是不同應變種類的鍺錫薄膜，並對薄膜品質進行深入的材料分析。
第三部分接著製作高電子遷移率的鍺錫電晶體。我們在較高錫比例的鍺錫鬆弛緩衝層上，成長具拉伸應變的鍺錫薄膜作為通道材料，同時為了降低源、汲極到基板的漏電流，我們提出了高台式電晶體結構，將源、汲極處的鍺錫薄膜回蝕，使源、汲極pn接面在鍺薄膜中形成，此結構能有效降低電晶體關閉電流，能準確地萃取載子遷移率。在不同應變種類的鍺錫電晶體中，拉伸應變能有效提升電子遷移率，主因是更多電子會聚集在擁有比較小等效質量的直接能帶中，使得電子遷移率得以提升。
為提升電晶體的效能，金屬/半導體接面電阻必須越小越好，但在N型鍺錫薄膜中，費米能階釘扎會使蕭特基能障無法藉由金屬功函數調變。我們製作蕭特基二極體，並萃取不同金屬與不同錫比例鍺錫薄膜間的蕭特基能障，發現錫比例10 %的鍺錫薄膜仍會有費米能階釘扎的現象出現，但蕭特基能障和能隙都會隨著錫比例增加而降低。此外，我們增加原位摻雜的濃度來降低能障的寬度，利用原位摻雜可以得到高載子濃度和載子活化率，可避免額外的退火製程以活化載子。利用refined transfer length method，我們萃取出不同摻雜濃度的鎳/N型鍺錫接面的接面電阻率，其接面電阻率隨摻雜濃度增加而降低。為更進一步降低接面電阻率，我們進行了熱退火使鎳和鍺錫形成鎳鍺錫合金，並得到N型鍺錫薄膜中最低的接面電阻率(1.5×〖10〗^(-7) -cm)。
此論文的最終部分，我們研究鍺錫材料在次微米電晶體的效能，我們利用原位摻雜的P型鍺錫薄膜製作無接面鍺錫鰭式電晶體。藉由改變不同的通道摻雜濃度與鰭寬研究電晶體的效能與短通道效應。並運用TCAD模擬，進一步將通道長度微縮，預測鍺錫電晶體對於次世代元件尺寸的電性表現。同時我們研究鍺錫薄膜的熱穩定性。分析鍺錫薄膜經由快速熱退火及微波退火後的晶格結構來判斷是否有錫稀出的現象出現，接著以離子佈植的方式進行外部摻雜，再分析鍺錫薄膜摻雜並退火候的晶格及電性表現，最後製作鍺錫二極體，分析其pn接面的特性，發現其逆偏電流會隨錫比例增加而增加。

關鍵字

化學氣相沉積 ； 鍺錫磊晶 ； 電子遷移率 ； 蕭特基能障 ； 接面電阻 ； 金氧半電晶體

並列摘要

GeSn is a promising material for high-performance CMOS logic devices due to its high carrier mobility and compatibility with Si VLSI. In this work, the high-quality epitaxial growth of GeSn films by chemical vapor deposition (CVD), a record high electron mobility of ~ 700 cm^2/V-s, electron Schottky barrier heights of metal/n-GeSn contacts with a record low contact resistivity of 1.5 x 10^-7 Ohm–cm^2 are demonstrated.
First, a modified CVD system for the GeSn epitaxial growth is introduced. A bubbler system for the SnCl_4 delivery is designed and installed, and high-quality GeSn films with a Sn fraction up to 12 % are successfully grown at 320 ℃. Ge_0.96Sn_0.04 n-MOSFETs are fabricated to investigate the electron mobility enhancement by modulating the strain in the GeSn films. GeSn films with different strain conditions such as compressive strained, strain relaxed, and tensile strained are grown. A novel mesa FET structure is proposed to effectively reduce the OFF current by forming recessed Ge source/substrate and drain/substrate junctions. A record high electron mobility of 698 cm^2/V·s is achieved in a tensile-strained Ge_0.96Sn_0.04 n-MOSFET, which could be attributed to the increased carrier population in the direct Γ band.
To further improve the device performance, the Schottky characteristics in metal/n-GeSn contacts are investigated. The Schottky barrier heights of metal/n-GeSn contacts with different metal workfunctions and Sn fractions are extracted, which shows the Fermi level pinning present in GeSn up to a Sn fraction of 10%. The Schottky barrier height could be effectively reduced with the Sn fraction due to the bandgap reduction in GeSn. By an in-situ doping technique to achieve high doping concentrations in the n-Ge0.9Sn0.1 films and forming a NiGeSn alloy by annealing, a record low contact resistivity of 1.5 × 10^-7 Ohm-cm^2 is achieved.
Junctionless p-Fin-FETs are also fabricated to evaluate the potentials of GeSn multigate structures for the future technology nodes. The effects of different fin widths and doping concentrations on the short-channel effects are investigated. TCAD simulation is performed and the results suggest that the fin width must be reduced to suppress the leakage and the high-k interface needs to further improved as the gate length scaled down to 20 nm. Last, the thermal stability of GeSn films is investigated to understand the thermal budget to improve the future manufacturing yields. Rapid thermal annealing and microwave annealing are performed and XRD results show the GeSn films with a lower Sn fraction or under compressive strain have better thermal stability. The dopant activation rate is limited by the phosphorus solid solubility in GeSn and crystal quality of GeSn. Furthermore, using microwave annealing can preserve more film quality with the same carrier activation rates.

並列關鍵字

Chemical vapor deposition ； GeSn epitaxy ； electron mobility ； Schottky barrier height ； Contact resistivity ； MOSFETs

參考文獻

[1] M. Liu, G. Han, Y. Liu, C. Zhang, H. Wang, X. Li, J. Zhang, B. Cheng, and Y. Hao, "Undoped Ge0.92Sn0.08 Quantum Well PMOSFETs on (001), (011) and (111) Substrates with in Situ Si2H6 Passivation: High Hole Mobility and Dependence of Performance on Orientation," 2014 Symposium on VLSI Technology, pp. 1-2, 2014.

[2] Y.-S. Huang, F.-L. Lu, Y.-J. Tsou, C.-E. Tsai, C.-Y. Lin, C.-H. Huang, and C. W. Liu, "First Vertically Stacked GeSn Nanowire pGAAFETs with Ion= 1850 μA/μm (Vov = Vds = -1V) on Si by GeSn/Ge CVD Epitaxial Growth and Optimum Selective Etching," 2017 IEEE International Electron Devices Meeting, pp. 37.5.1-37.5.4, 2017.

[3] C. Schulte-Braucks, S. Glass, E. Hofmann, D. Stange, N. von den Driesch, J. M. Hartmann, Z. Ikonic, Q. T. Zhao, D.Buca, and S. Mantl, "Process Modules for GeSn Nanoelectronics with High Sn-contents," Solid-State Electronics, vol. 128, pp. 54-59, 2017.

[4] H.-S. Lan, and C. W. Liu, "Band Alignments at Strained Ge1-xSnx/Relaxed Ge1-ySny Heterointerfaces," Journal of Physics D: Applied Physics, vol. 50, no. 13, p. 13LT02, 2017.

[5] S. Wirths, D. Buca, and S. Mantl, "Si–Ge–Sn Alloys: From Growth to Application," Progress in crystal growth and characterization of materials, vol. 62, no. 1, pp. 1-39, 2016.