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  • 學位論文

具離散時間及無限脈衝響應濾波器回授之兩百億位元每秒可適性決策回授等化器

A 20Gb/s Adaptive Decision Feedback Equalizer with 1 Discrete-time Tap and 1 IIR Feedback

指導教授 : 劉深淵
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摘要


在有線通訊系統中,隨著資料傳輸速率不斷提升,傳輸通道所產生的符際效應(inter-symbol interference,ISI)越來越嚴重,使等化器(equalizer)越顯重要。此外通道衰減的特性會隨著通道的材質與長度不同而改變,因此,應用於等化器的可適性方法在實際應用中是必須的。 本論文中提出一個兩百億每秒的無限脈衝響應濾波器之決策回授等化器,採用電荷導向式邏輯電路提升功率效益。並且提出一個基於SS-LMS的迴路控制演算法。在40奈米製程的模擬當中,此可適性等化器在20Gbps的PRBS 27-1資料可以補償小於6.71dB的通道損耗,決策回授等化器功耗為12.3mW,佈局面積為0.0712mm2。

並列摘要


In wireline communication, as the data rate increases, inter-symbol interference (ISI) generated by the transmission channel has become more and more serious, making the equalizer more important. In addition, the attenuation characteristics of the channel will change with the material and length of the channel. Therefore, the adaptation method applied to the equalizer is necessary in practical applications. In this paper, a decision feedback equalizer with a 20Gbps infinite impulse response filter is proposed, which uses a charge-steering logic circuit to improve power efficiency. In addition, a loop control algorithm based on SS-LMS is proposed. In the simulation of the 40nm process, the 20Gbps PRBS 27-1 data of this adaptive equalizer can compensate channel loss up to 6.71dB. Power consumption of the decision feedback equalizer is 12.3mW, and the layout area is 0.0712mm2.

參考文獻


[1] K.-Y. Chen, W.-Y. Chen and S.-I. Liu, "A 0.31pJ/bit 20Gb/s DFE with 1 discrete tap and 2 IIR filters feedback in 40nm-LP CMOS", IEEE Trans. Circuits and Syst. II: Exp. Briefs, vol. 64, no. 11, pp.1282-1286, Nov. 2017.
[2] J. W. Jung, and B. Razavi, “A 25 Gb/s 5.8mW CMOS equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515–526, Feb. 2015.
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[5] S. Ibrahim, and B. Razavi, “Low-power CMOS equalizer design for 20-Gb/s systems,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1321–1336, June 2011.

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