超薄氧化層純水補償技術及氫對ONO介電層可靠度之影響

在這個研究中，我們提出了掃描頻率陽極氧化(Scanning-frequency Anodization)修補的方法來修補超薄二氧化矽氧化層(SiO2)以增進其特性。我們所使用的掃描頻率為20赫茲到200k赫茲。在經過掃描頻率修補之後，厚度為18Å的二氧化矽氧化層，其在-2V之閘極漏電流密度(Gate Leakage Current Density)為1.5A/cm2，較相同厚度未經修補之二氧化矽氧化層降低了75%。除此之外，在經過掃描頻率陽極氧化修補之後，其界面缺陷密度(Dit)也減少了20%。因為高介電常數(High-k)材料的氧化鋁(Al2O3)有在低電場下低漏電流及在高電場下高穿隧電流的特性，因此我們用來取代MONOS型式非揮發性記憶體中的二氧化矽氧化層。我們用-16V抹除(Erase)10ms，可達到6V的平帶電壓(Flatband Voltage)横移。其10年投影預測之寫入(Program)/抹除電壓差，在室溫及85oC下，分別為5.3V及4.9V。我們在研究中也發現，在400oC或更高的溫度之下以氫氣烘烤，能夠抹除以氮化矽為儲存層的電荷儲存記憶體中的儲存電子。無論原先的平帶電壓為何，在元件周邊區域經過高溫氫處理之後，所有的平帶電壓值都會相同。但氫只會影響有儲存電荷的區域，若元件中沒有儲存電荷，則不受影響。此特性可以解決紫外光或是電漿所引起的周邊電荷儲存問題。經過紫外光照射而有周邊電荷儲存的記憶體元件在400oC下僅需15分鐘即可抹除其儲存電荷。

關鍵字

超薄氧化層；高介電常數閘極介電質；電荷儲存快閃記憶體；氫抺除

並列摘要

In this work, a method named scanning-frequency anodization (SF-ANO) was proposed to improve the quality of ultra-thin thermally grown SiO2. The frequency condition of SF is from 20Hz to 200kHz. After SF-ANO treatment, the gate leakage current of 18Å SiO2 is 1.5A/cm2 at -2 V, which is 75% off compare with the device with the same thickness without ANO treatment. Besides, 25% reduction in interface trap density (Dit) can also be observed after SF-ANO treatment. High performance trap-less MAD Al2O3 was then used to replace the tunnel and block layer in MONOS type flash memory because of the suppressed gate leakage current at low electric field and enhanced tunneling current at high electric field, and a MANAS stack is obtained. 6V erase window can be achieved in 10ms by using -16V erase voltage. Besides, the 10-year projected retention window is as large as 4.9V at 85oC, and 5.3V at RT. Hydrogen is found to invade into nitride-based charge trapping memory stack from the edge and neutralize the trapping electrons as baking at temperature of 400oC or above. Regardless of the programmed flatband voltages (VFB) are, all the devices had the same VFB at the edge of the devices. Hydrogen invasion occurs only in the programmed ONO devices; a non-programmed ONO device would not be affected. The experimental results are suggested to solve the problems of UV or plasma induced charge trapping. The UV induced trapping charges can be eliminated in 15 minutes as baking at 400oC.

並列關鍵字

Ultra-thin oxide ； high-k gate dielectric ； charge trapping flash memory ； hydrogen erase

參考文獻

[83]. A.T. Krishnan, C. Chancellor, S. Chakravarthi, P.E. Nicollian, V. Reddy, A. Varghese, R.B. Khamankar, and S. Krishnan, “ Material Dependence of Hydrogen Diffusion: Implication for NBTI Degradation,” IEEE IEDM Technical Digest, 705-708, 2005

[61]. Y. Shin, J. Choi, C. Kang, C. Lee, K.T. Park, J.S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H.J. Cho, and K. Kim, “A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” IEEE IEDM Technical Digest, pp. 337-340, 2005.

[73]. Y.H. Shih, S.C. Lee, H.T. Lue, M.D. Wu, T.H. Hsu, E.K. Lai, J.Y. Hsieh, C.W. Wu, L.W. Yang, K.Y. Hsieh, K.C. Chen, R. Liu, and C.Y. Lu, “Highly Reliable 2-bit/cell Nitride Trapping Flash Memory Using a Novel Array-Nitride-Sealing (ANS) ONO Process,” IEEE IEDM Technical Digest, 559-562, 2005

[2]. Y. Zhao, K. Kita, K. Kyuno, and A. Toriumi, “Band Gap Enhancement and Electrical Properties of La2O3 Films Doped with Y2O3 as High-k Gate Insulators ”, Applied Physics Letters, Vol. 94, pp. 042901, 2009

[4]. E. Nadimi, C. Golz, M. Trentzsch, L. Herrmann, K. Wieczorek, and C. Radehaus, “Tunneling Effective Mass of Electrons in Lightly N-Doped SiOxNy Gate Insulators,” IEEE Transactions on Electron Devices, pp. 2462-2468, 2008

國際替代計量

超薄氧化層純水補償技術及氫對ONO介電層可靠度之影響

全文下載

主題瀏覽