應用於無線通訊之低雜訊放大器之設計與實作

Design and Implementation of Low-Noise Amplifier for Wireless Communications

陳科后(ke-Hou Chen)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10423

摘要

隨著CMOS製程的進步以及對高速資料傳輸的需求增加，不同的無線傳輸規格，像是超寬頻系統和藍芽等等也越來越普及。在無線接收機中，低雜訊放大器是一個關鍵的電路。雖然相關的電路技巧已發展多年，我們仍然需要新的技巧來提升電路的效能。因此在這本論文裡，我們提出了一些電路技巧來解決低雜訊放大器在各種無線通訊中所遇到的問題。
首先，我們實現了一個適用於超寬頻系統的低雜訊放大器。在此電路中，第一級用來提供寬頻匹配及低頻增益，第二級用來提供高頻增益，藉此達到整體的寬頻響應。以0.18微米CMOS製作，此晶片最大可提供12.4 dB功率增益，具有0.4–10-GHz的頻寬，最小雜訊指數是4.4 dB。此晶片在1.8 V供應電壓下消耗12 mW。由於整個電路只使用兩個電感，所以晶片面積僅有0.42 mm2。
在寬頻放大器中，很難同時得到好的輸入匹配和雜訊。因此，我們提出一個改善雜訊相消技巧的方法，並以此技巧實現在65奈米的CMOS無電感寬頻放大器中。供應電壓為1 V之下，第一個電路提供了高達10 GHz的頻寬，並具有10.5 dB的功率增益，最小雜訊指數是2.7 dB，消耗功率為13.7 mW。第二個電路提供了10.7 dB的功率增益，最小雜訊指數是2.9 dB。雖然頻寬只有5.2 GHz，但消耗功率僅有7 mW。
之後，為了消除高頻放大器的雜訊，在65奈米的CMOS製程中實現了一個58 GHz的雜訊相消低雜訊放大器。把雜訊相消的技巧使用在微波頻段中，得到12.2 dB的功率增益和4.6 dB的雜訊指數。此晶片在1 V供應電壓下消耗17 mW，晶片面積僅有0.2 mm2。
最後是一個操作在2.4 GHz，具有輸入匹配校正的電路。藉由一個放大器/振盪器雙模電路，並共用接收機中的數位電路，使其在頻域上校正。輸入反射係數為±50MHz, 校正時間只有2.8微秒。

關鍵字

低雜訊放大器 ； 寬頻 ； 雜訊相消

並列摘要

With the progress of the CMOS technologies and the increasing demand for high-speed data communications, several specifications such as ultra-wideband (UWB) and Bluetooth become more and more popular. In a wireless receiver, the LNA is a key component. Though relating techniques have prospered for years, new circuit techniques are still desired to improve the performances of the LNA. Therefore, in this dissertation, we propose some techniques to overcome the problems of the LNA in wireless communications.
First, a LNA for UWB system is presented. In this circuit, the first stage provides wideband input matching and lower −3dB gain, the second stage provides higher −3dB gain; hence the wideband input matching and gain are both achieved. Fabricated in 0.18μm CMOS, it achieves a maximum power gain of 12.4 dB with a bandwidth of 0.4–10-GHz, and a minimum NF of 4.4 dB. It consumes 18 mW from a 1.8 V supply voltage. Using only two inductors, it occupies an area of only 0.42 mm2.
Tradeoff exists between input matching and noise in a wideband amplifier. Therefore, a gain-enhanced noise-canceling technique is used in inductorless LNAs and implemented in 65-nm CMOS process. Under a supply voltage of 1 V, the first LNA achieves a power gain of 10.5 dB, a bandwidth of 10 GHz, and a minimum NF of 2.7 dB. It consumes 13.7 mW. The second LNA provides a power gain of 10.7 dB and a minimum NF of 2.9 dB. Although the bandwidth is only 5.2 GHz, the power consumption is as small as 7 mW.
Hereafter, a 58-GHz noise-canceling LNA is realized in 65-nm CMOS process. Using the noise-canceling technique in millimeter-wave band, the LNA achieves a power gain of 12.2 dB, and a NF of 4.6 dB. It consumes 17 mW from a 1 V supply voltage. The chip area is only 0.2 mm2.
Finally, a 2.4-GHz LNA with input impedance calibration is realized in 0.18-

並列關鍵字

Low-noise amplifier ； wideband ； noise-canceling

參考文獻

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