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  • 學位論文

應用於第五世代行動通訊之高輸出功率及高效率CMOS功率放大器研究

Research on High Output Power and High Efficiency CMOS Power Amplifier for 5G Mobile Communication

指導教授 : 陳中平
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摘要


近年來,隨著第五世代行動通訊發展,高資料量傳輸意味著需要更高的頻寬以及更快的速率。毫米波頻段因能滿足高資料傳輸,因此相對應的研究與應用與日俱增。本論文分為兩大部分,第一部分是一個Ka頻段疊接組態功率放大器,第二部分是一個Ka頻段堆疊組態功率放大器,皆採用90奈米互補式金屬氧化物半導體製程設計與製作。 第一部分採用電流式功率結合變壓器來降低振福誤差及相位誤差,電中和技術被用來穩定電路,整體晶片面積為0.49 mm^2以及核心面積為0.2 mm^2。量測中發生非預期的震盪現象,並討論震盪原因。 第二部分同樣採用電流式功率結合變壓器以及電中和技術。除此之外利用並聯在汲極以及源極的回授電容,來抵銷因堆疊特性所產生的寄生電容。旁路電路使用片狀分層架構使得佈局上擁有更好的彈性,整體晶片面積為0.563 mm^2以及核心面積為0.198 mm^2。連續載波量測顯示在28GHz下,小訊號增益17.2 dB,大訊號飽和輸出功率為23.8 dBm下,功率附加效率為23%。在調變訊號量測顯示,在64-QAM單頻載波調變訊號中,傳輸資料量為1.5/3 Gbps在方均根錯誤向量誤差小於-25dB下,此功率放大器可達到 17.1/16.8 dBm的平均輸出功率以及5.5/5.1 % 平均功率附加效率。在64-QAM正交分頻多工(OFDM)調變訊號中,通道頻寬為100, 200, 300, 400, 800 MHz在方均根錯誤向量誤差小於-25dB條件下,此功率放大器可達到 15.9/16.3/16.5/16.8, 16.3-dBm的平均輸出功率以及4.2/4.7/4.8/5.1/4.7 % 平均功率附加效率。

並列摘要


In recent years, fifth-generation communication industry develops. The demand of high data rate transmission means the wider bandwidth and faster rate are required. Since millimeter wave can meet high data transmission. Therefore, the corresponding research and applications are increasing day by day. The thesis consists of two part, the first part is applying for Ka-band cascode power amplifier and the second part is applying for Ka-band 3-stack power amplifier. Both are fabricated and designed in CMOS 90-nm process. In the first part, transformer-based current-type power combiner is adopted to minimize amplitude and phase imbalance. Neutralization is used to improve overall stability. The whole chip area is 0.49 〖mm〗^2 and core area is 0.2 〖mm〗^2. In experiment, undesired oscillations were observed. We discuss potential problems resulting in oscillations. In the second part, transformer-based current-type power combiner and neutralization also are applied. Moreover, a shunt feedback capacitor is utilized to offset the parasitic capacitance resulted from stack topology. Bypass capacitors are designed by interdigitated structure which make layout more flexible. The whole chip area is 0.562 〖mm〗^2 and core area is 0.198 〖mm〗^2. In continuous-wave measurement, the proposed 3-stack PA achieves 17.2 small-signal gain, 23.8-dBm saturation power with 23% peak PAE at 28 GHz. In single-carrier 64-QAM signal with 1.5/3-Gbps data rate experience, the proposed PA achieves -25 dB rms EVM with average output power of 17.1/16.8 dBm and average PAE of 5.5/5.1%. For 64-QAM OFDM signal with RFBW of 100, 200, 300, 400 and 800 MHz, the proposed PA achieves -25 dB rms EVM with average output power of 15.9/16.3/16.5/16.8/16.3-dBm and average PAE of 4.2/4.7/4.8/5.1/4.7%.

參考文獻


[1] Y. Chen, T. Tsai, J. Tsai and T. Huang, "A 38-GHz-Band Power Amplifier with Analog Pre-distortion for 1600-MHz Transmission Bandwidth 64-QAM OFDM Modulated Signal," 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019, pp. 312-315.
[2] J. Lin, Y. Lin, Y. Hsiao and H. Wang, "A K-band transformer-based power amplifier with 24.4-dBm output power and 28% PAE in 90-nm CMOS technology," 2017 IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, USA, 2017, pp. 31-34.
[3] Y. Zhang and P. Reynaert, "A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS," 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, USA, 2017, pp. 33-36.
[4] K. Chiang, T. Tsai, I. Huang, J. Tsai and T. Huang, "A 27-GHz Transformer Based Power Amplifier with 513.8-mW/mm2 Output Power Density and 40.7% Peak PAE in 1-V 28-nm CMOS,"2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019, pp. 1283-1286.
[5] S. Shakib, M. Elkholy, J. Dunworth, V. Aparin and K. Entesari, " A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 44-45.

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