基於機器學習的神經形態晶片測試樣本生成

Machine Learning-­Based Test Pattern Generation for Neuromorphic Chips

曾筱茵(Hsiao-Yin Tseng)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202101660

摘要

隨著機器學習的興起，許多物聯網裝置使用到 AI 技術。然而，運行機器學習需要大量的計算，導致裝置的高功耗，而物聯網裝置通常擁有功耗的限制。為了滿足邊緣設備的功耗限制，仿生神經形態晶片成為熱門話題，因而需求倍增。於是，高效的製造測試成為一個問題。傳統測試方法無法應用在神經形態晶片上面，因為有一些神經形態晶片沒有掃描鏈。然而，傳統的神經形態晶片功能測試存在測試長度長、錯誤覆蓋率低的問題。在這項研究中，我們提出了一種具有行為錯誤模型的基於機器學習的測試樣本生成技術。我們使用對抗式攻擊的概念來生成高效的測試樣本，以減少現有功能測試模式的測試長度和提高其錯誤覆蓋率。我們在 MNIST 上訓練的兩種不同的脈衝神經網絡模型上證明了所提出技術的有效性。與傳統的功能測試相比，我們提出的 ATPG 技術將測試長度減少了 3,750 倍到 4,784 倍，並且在三個神經元錯誤模型和一個突觸錯誤模型提高了 14.38% 到 56.5% 的錯誤覆蓋率。而我們的技術不只適用於脈衝神經網絡，也適用於其他機器學習模型。最後，我們提出了一種方法來解決突觸錯誤模型的可擴展性問題，與對所有突觸錯誤進行 ATPG 相比，運行時間減少了 25.7 倍。

關鍵字

神經形態晶片 ； 脈衝神經網絡 ； 測試樣本生成 ； 對抗式攻擊

並列摘要

With the rise of machine learning, there are many low power edge devices integrated with AI. However, performing machine learning tasks needs intensive computation, re­sulting in high power consumption. In order to meet the power consumption limitation on edge devices, bio­inspired neuromorphic chips have become a hot topic, and hence the demand has skyrocketed. Thus, efficient manufacturing testing becomes an issue. Con­ventional testing cannot be applied because some neuromorphic chips do not have scan chains. However, traditional functional testing for neuromorphic chips suffers from long test length and low fault coverage. In this work, we propose a machine learning-­based test pattern generation technique with behavior fault models. We use the concept of ad­versarial attack to generate efficient test patterns, which reduce test length and improve the fault coverage of existing functional test patterns. The effectiveness of the proposed technique is demonstrated on two different Spiking Neural Network models trained on MNIST. Compared to traditional functional testing, our proposed ATPG technique re­ duces test length by 566x to 8,824x and improves fault coverage by 8.1% to 86.3% on three neuron fault models and two synapse fault models. Moreover, in addition to SNN, our proposed ATPG is applicable to other machine learning models. Finally, we propose a methodology to solve the scalability issue for the synapse fault models, resulting in 25.7x run time reduction compared with ATPG on all synapse faults.

並列關鍵字

neuromorphic chip ； Spiking Neural Network ； test pattern generation ； adversarial attack

參考文獻

[1] I. J. Goodfellow, J. Shlens, and C. Szegedy, “Explaining and harnessing adversar­ ial examples,” in 3rd International Conference on Learning Representations, ICLR 2015, San Diego, CA, USA, May 7­9, 2015, Conference Track Proceedings (Y. Ben­ gio and Y. LeCun, eds.), 2015.

[2] J. Backus, “Can programming be liberated from the von neumann style? a functional style and its algebra of programs,” Commun. ACM, vol. 21, p. 613–641, Aug. 1978.

[3] F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez­Icaza, J. Arthur, P. Merolla, N. Imam, Y. Nakamura, P. Datta, G.­J. Nam, B. Taba, M. Beakes, B. Brezzo, J. B. Kuang, R. Manohar, W. P. Risk, B. Jackson, and D. S. Modha, “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE Transactions on Computer­Aided Design of Integrated Circuits and Systems, vol. 34, no. 10, pp. 1537–1557, 2015.

[4] M. Davies, N. Srinivasa, T.­H. Lin, G. Chinya, Y. Cao, S. H. Choday, G. Dimou,

P. Joshi, N. Imam, S. Jain, Y. Liao, C.­K. Lin, A. Lines, R. Liu, D. Mathaikutty, S. McCoy, A. Paul, J. Tse, G. Venkataramanan, Y.­H. Weng, A. Wild, Y. Yang, and H. Wang, “Loihi: A neuromorphic manycore processor with on­chip learning,” IEEE Micro, vol. 38, no. 1, pp. 82–99, 2018.