分離式電容陣列連續漸進式暫存器類比數位轉換器之自我交互測試及校正技術

A Mutual Characterization Based Split SAR ADC Self-testing and Calibration Technique

林浩任(Hao-Jen Lin)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.11046

摘要

本篇論文中，我們針對分割電容陣列架構連續逼進式類比數位轉換器提出自我交互測試及校正技術。該類比數位轉換器使用橋接電容，將原本的電容陣列分割成數個子電容。透過加入切換裝置以實現子電容之間的交互測試，可得到針對該子電容陣列的特性描述，利用該特性描述可更進一步得到單個子電容陣列上每顆電容的等效權重。如此一來便可利用每顆電容的等效權重來模擬該數位類比轉換器的操作行為，並進行其效能評估，同時幫助進行數位校正以提高其線性度。以下幾點為所提出測試及校正技術的優勢：
1) 藉由該類比數位轉換器獨特的分割電容架構，可降低測試所需額外的面積成本。
2) 類同於正常操作模式的測試步驟，使測試過程簡單並且快速。
3) 透過等效權重模擬該轉換器操作行為，能更快得到差動非線性與積分非線性。
4) 可利用等效權重進行外部的數位校正，以提升線性度並同時提高生產良率。
本篇論文所提出的測試方法與校正技術，皆經過縝密的數值分析及行為模擬，模擬數據也反映所得的等效權重與模擬的操作行為非常接近其實際值，且校正過後其線性度更大為提升。

關鍵字

連續漸進式暫存器類比數位轉換器 ； 數位類比轉換器測試 ； 數位類比轉換器校正 ； 電容不匹對

並列摘要

In this thesis, we present a self-testing technique and calibration methodology for split-capacitor–array Successive Approximation Register analog-to-digital converter (SAR ADC). Taking advantage of the split-capacitor-array architecture, the mutual characterization incurs much less area overhead than previous work. The capacitor array is reconfigured in functional-like characterization of proposed self-testing, so that the equivalent weights of each bit in one sub-array can be extracted with the help of the other sub-arrays. From the derived equivalent weights, the ADC performance can then be simulated and estimated much faster than previous work to get the Differential Non-Linearity/Integrated Non-Linearity (DNL/INL) information. Moreover, the equivalent weights can be regarded as calibration parameter, so that the non-linearity induced by capacitor mismatch can be further calibrated via external digital calibration. Simulation results show the high DNL/INL estimation accuracy of the proposed technique and substantially improvement between before and after calibration.

並列關鍵字

SAR ADC ； ADC testing ； ADC calibration ； capacitor mismatch ； mixed-signal testing

參考文獻

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