Title

應用於晶片間傳輸之時脈誤差校正電路設計

Translated Titles

Design of a Clock-Deskew Buffer Circuit for Chip-to-Chip Links

DOI

10.6845/NCHU.2012.00136

Authors

莊璦嘉

Key Words

時脈誤差校正緩衝器 ; 雙向傳輸緩衝器 ; 延遲鎖定迴路 ; 低電壓差動訊號傳輸器 ; clock-deskew buffer ; bidirectional buffer ; delay-locked loop ; low-voltage differential signaling (LVDS) transmitter

PublicationName

中興大學電機工程學系所學位論文

Volume or Term/Year and Month of Publication

2012年

Academic Degree Category

碩士

Advisor

楊清淵

Content Language

繁體中文

Chinese Abstract

近年來隨著CMOS製程技術的快速發展,高整合密度之超大型積體電路系統的需求呈指數性成長,且系統時脈頻率也大幅提高,各電路模組間時脈抖動的問題也日趨嚴重。過大的時脈抖動將會降低系統的實行速度和可靠度,因此如何降低時脈誤差進而使各模組間同步變成了一個重要課題。 本論文介紹了數種可用來修正時脈誤差的架構,並提出一種採用栓鎖式雙延遲鎖定迴路技術的時脈誤差校正電路,在不需仿真傳輸通道與估算偏移量下,能自行針對各時脈間的偏移進行校正。此外藉由低電壓差動傳輸器當作傳輸介面,使其能操作在較高頻率。其製程是使用台積電0.18微米互補式金氧半導體製程,晶片面積為0.964mm×0.975mm,輸出頻率範圍為750MHz~1.5GHz。當初輸入頻率為1.5GHz且操作電壓為1.8V時,輸出時脈之峰對峰值抖動為8.89ps且消耗功率為33mW。 另外,在本篇論文中還提出一個具寬頻操作之時脈誤差校正電路,其中寬頻操作是使用多頻帶壓控延遲線來完成。其製程同樣是使用台積電0.18微米互補式金氧半導體製程進行設計與模擬,經由模擬結果可知此時脈誤差校正電路可工作在20MHz~2GHz的頻率範圍。當初輸入頻率為2GHz且操作電壓為1.8V時,輸出時脈之峰對峰值抖動為9.81ps且消耗功率為40mW,晶片面積為1.39mm×1.39mm。

English Abstract

With the rapid advances in CMOS technology, the demand for highly integrated VLSI circuit has grown exponentially in recent years. As the system frequency is rising, the problem of timing jitter for circuit modules is more serious. It will decrease the speed and the responsibility, if the timing jitter is too high. So in modern high-speed systems, the skew-free distribution of clocks is very critical for synchronous circuits and the clock-skew problem will become a significant subject. In this thesis, several architectures which may be used to correct clock skew are introduced. A novel clock-deskew buffer with a latch-based dual delay-locked loop (LBD-DLL) technique is proposed to synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. The LBD-DLL can operate in high frequencies by using the low-voltage differential architecture for the interfaced I/Os. Fabricated in TSMC 0.18-um CMOS process, the circuit can provide the output frequency range of 750MHz to 1.5GHz and the chip area is 0.964mm×0.975mm. When the operation frequency is 1.5GHz, the peak-to-peak jitter of the output clock is 8.89ps and total power dissipation is 33mW under a 1.8-V supply voltage. Furthermore, in order to provide wide operation range, a wide-range clock-deskew buffer is proposed in the second word. The wide-range operation is achieved in multi-band voltage controlled delay line. This chip is also fabricated in TSMC 0.18-um CMOS process. From the simulation results, we can demonstrate that this clock-deskew buffer can operate from 20MHz to 2GHz. When the operation frequency is 2GHz, the peak-to-peak jitter of the output clock is 9.81ps and total power dissipation is 40mW under a 1.8-V supply voltage. The chip area is 1.39mm×1.39mm.

Topic Category 電機資訊學院 > 電機工程學系所
工程學 > 電機工程
Reference
  1. [5]C. Y. Yang and S. I. Liu, “A one-wire approach for skew-compensating clock distribution based on bidirectional techniques,”IEEE Journal of Solid-State Circuits, vol. 36, pp. 266-272, Feb. 2001.
    連結:
  2. [7]A. Coban, M. H. Koroglu, and K. A. Ahmed, “A 2.5-3.125Gb/s quad transceiver with second order analog DLL-based CDR’s,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1940-1947, Sep. 2005.
    連結:
  3. [8]G. Chien and P. R. Gray, “A 900MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1995-1996, Dec. 2000.
    連結:
  4. [9]G. K. Dehng, J. M. Hsu, C. Y. Yang and S. I. Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, No. 8, pp. 1128-1136, Aug. 2000.
    連結:
  5. [12]S. K. Kao and S. I. Liu, “ A Delay-Locked Loop With Statistical Background Calibration,” IEEE Transactions on Circuits and Systems-II:Express Briefs, vol. 55, pp. 961-965, Oct. 2008.
    連結:
  6. [13]J. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics Letters, pp. 1222-1223, June 1993.
    連結:
  7. [14]H. H. Chang, J. W. Lin, C. Y. Yang and S. I. Liu, “A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002
    連結:
  8. [15]M. G. Johnson, E. L. Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct. 1988.
    連結:
  9. [17]Y. Moon, J. Choi, K. Lee, D. K. Jeong, M. K. Kim, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 377-384, March 2000.
    連結:
  10. [20]T. Saeki, K. Minami, H. Yoshida and H. Suzuki, "A Direct-skew-detect Synchronous Mirror Delay for Application Specific Integrated Circuits," IEEE Journal of Solid-State Circuits, vol. 34, pp. 372-379, March 1999.
    連結:
  11. [22]S. I. Liu, J. H. Lee, and H. W. Tsao, "Low-Power Clock-Deskew Buffer for High-Speed Digital Circuits," IEEE Journal of Solid-State Circuits, vol. 34, pp. 554-558, April 1999.
    連結:
  12. [24]K. McBirde and C. Aswell, "Clock Deskewing Apparatus Including Three-Input Phase Detector," US patent:5,594,376, Jan. 1997.
    連結:
  13. [30]C. N. Chuang, and S. I. Liu, “A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop,” IEEE Transactions on Circuits and Systems-II:Exp. Briefs, vol. 56, no. 11, Nov. 2009.
    連結:
  14. [32]G. Esch, Jr. and T. Chen, “Near-Linear CMOS I/O Driver With Less Sensitivity to Process, Voltage, and Temperature Variations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, Nov. 2004.
    連結:
  15. [33]M. Bazes, “ Two Novel Fully Complementary Self-biased CMOS Differential Amplifiers ”, IEEE Journal of Solid-State Circuits, vol. 26, pp. 165-168, Feb. 1991.
    連結:
  16. [34]S. K. Kao and S. I. Liu, “A Delay-Locked Loop With Statistical Background Calibration,” IEEE Transactions on Circuits and Systems- II:Exp. Briefs, vol. 55, no. 10, Oct. 2008.
    連結:
  17. [36]Y. H. Tu, H. H. Chang, C. L. Hung and K. H. Cheng, “A 3 GHz DLL-Based Clock Generator with Stuck Locking Protection,” Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, Dec. 2010.
    連結:
  18. [37]Y. G. Chen, H. W. Tsao and C. S. Hwang, “A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012.
    連結:
  19. [38]B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2000.
    連結:
  20. [39]H. H. Chang, J. Y. Chang, C. Y. Kuo and S. I. Liu, “ A 0.7-2-GHz Self-Calibrated Multiphase Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, May. 2006.
    連結:
  21. [40]K. C. Kuo and Y. H. Hsu, “A Low Power Multi-band Selector DLL with Wide-Locking Range,” Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pp 25-28, June 2008.
    連結:
  22. [41]M. J. Kim and L. S. Kim, ” A 100MHz-to–1GHz Open-Loop ADDLL with Fast Lock-Time for Mobile Applications,” Custom Integrated Circuits Conference (CICC), 2010 IEEE, Sep. 2010.
    連結:
  23. [1]“3DIC & TSV Report:Cost, Technologies & Markets,”Yole Development,http://yole.fr/pagesAn/products/Report_sample/3DIC.pdf, Nov.2007.
  24. [2]Y. Lee, N. C. Cheng, C. Y. Yang, J. J. Chen and Y. H. Chu,“Method and Apparatus for Clock Skew Compensation,” Industrial Technology Research Institute(ITRI), Sep. 2010.
  25. [3]A. H. Atrash, “Data Bus Deskewing System in Digital CMOS Technology,” Ph.D. Dissertation, Georgia Institute of Technology, May 2004.
  26. [4]J. Y. Chueh, “A Delay Locked Loop Using Modified Binary Search Algorithm,”M.S. thesis, National Taiwan University, June 2001.
  27. [6]Y. Lee, “A Clock/Data Recovery Circuit and an Efficient I/O for Chip-to-Chip Communication,” M.S. thesis, National Chung Hsing University, July 2005.
  28. [10]T. J. Gomm, “Design Delay-Locked Loop with a DAC-Controlled Analog Delay Line,” M.S. thesis, College of Graduate Studies University of Idaho, March 2001.
  29. [11]J. W. Lin, “Design and realization of analog delay-locked loops,” M.S. Thesis, National Taiwan University, June 2001.
  30. [16]J. Cheng, “A Delay-Locked Loop For Multiple Clock Phase/Delays Generation,” Ph.D. Dissertation, Georgia Institute of Technology, Dec. 2005.
  31. [18]劉深淵、楊清淵,“鎖相迴路,”滄海書局, Nov. 2006.
  32. [19]Hongjiang Song, "Digital Delay Locked Loop for Adaptive De-skew Clock Generation," US patent:6,275,555, Aug. 2001.
  33. [21]B. L. Brown and D. R. Brown, "Clock Skew Circuit," US patent:6,005,430, Dec. 1999.
  34. [23]Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, "Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface," IEICE Transactions Electron., vol. E79-C, no. 6, pp. 798-807, June 1996.
  35. [25]A. H. Atrash, and B. Butka, “ A Technique to Deskew Differential PCB Traces,” ISCAS’04 Proceedings of the 2004 International Symposiumon, Page(s):II-565-568, vol. 2, May 2004.
  36. [26]C. Y. Yang, "One-Wire Approach and Circuit for Clock-Skew Compensating," US patent:6,754,841, Jun. 2004.
  37. [27]A. Kumar, “A Wide Dynamic Range High-Q High-Frequency Bandpass Filter With an Automatic Quality Factor Tuning Scheme,” M.S. Thesis, Georgia Institute of Technology, May 2009.
  38. [28]M. T. Tsai and Y. Z. Liang, “A 65nm CMOS 150MHz-2GHz Wide Range PLL,” Industrial Technology Research Institute(ITRI), Oct. 2010.
  39. [29]S. Han, J. Jin and C. Mao, “A Full-Swing Charge Pump With Zero Phase Offset,” Microelectronics & Electronics, PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in, pp. 298-301, Jan. 2009.
  40. [31]K. Abugharbieh, S. Krishnan, J. Mohan, V. Devnath and I. Duzevik, ”An Ultralow-Power 10-Gbits/s LVDS Output Driver,” IEEE Transactions on Circuits Systems-I: Regular Papers, vol. 57, no. 1, Jan. 2010.
  41. [35]K. Fong, Y. C. Hung, Z. Z. Chen and T. C. Lee, “An All-Digital De-skew Clock Generator for Arbitrary Wide Range Delay,” Circuits and Systems (APCCAS), 2010 IEEE Asian Pacific Conference on, Dec. 2010.