Translated Titles

A Method of Correcting the Shift Error of Multilevel Flash Memory by the Skill of Gray Code





Key Words

格雷碼 ; 快閃記憶體 ; multilevel flash ; gray coding ; shift level



Volume or Term/Year and Month of Publication


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Content Language


Chinese Abstract

現今的快閃記憶體(flash memory),為了增加記憶體儲存密度 ,就會犧牲元件可靠度(reliability)。因此,維持元件可靠度的問題在多值快閃記憶體(multilevel flash memory, ML)上是非常重要的。在此篇論文中,我們提出一個格雷編碼(Gray coding)的架構,來減少多值快閃記憶體位移(shift level)所產生的位元錯誤,並且可以有效的提高多值快閃記憶體可靠度。 使用格雷編碼可以將位移錯誤的位元數控制在某一範圍,有效的降低錯誤更正碼(error correction codes, ECC)所需的檢查碼數 量,進而減少檢查碼(check code)所耗用的記憶體、面積(area pena- lty)和峰值功率消耗(peak power dissipation)。最後我們使用C語言來驗証模擬,證明格雷編碼可以有效提高錯誤更正碼的更正成功機率。

English Abstract

In new-generation Flash memories, in order to economize the use of density of a cell that certainly will decrease the reliability of device. Thus, it is very important that how to maintain and improve the reliability of device in multilevel flash. In this work, we propose a new scheme of gray coding to reduce error bits caused by shift level in multilevel flash. Furthermore, the proposed scheme also can effectively enhance the reliability of multilevel flash. In our experiment results, gray coding method can limit the error bits caused by shift level in a scope, and validly reduce check bit number for error correction code. Moreover, it diminishes memory of error check code, area penalty and peak power dissipation.

Topic Category 基礎與應用科學 > 資訊科學
電機資訊學院 > 資訊科學與工程學系所
  1. [3] K. Itoh, “VLSI Memory Chip Design,” Springer pp. 46-47, 2001.
  2. [6] C. Calligaro, A. Manstretta, A. Pierin and G Torelli,“Comparative Analysis of Sensing Schemes for Multilevel Non-Volatile Memories,” Proc. IEEE Int. Conf. on Innovative System in Silicon, pp. 266-273, Oct. 1997.
  3. [7] T. S. Jung, Y. J. Choi, K. D. Suh, “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” Solid-State Circuits Conference, Digest of Technical Papers. 43rd IEEE ISSCC96, 1996.
  4. [8] H. Nobukata, S. Takagi, K. Hiraga, “A 144-Mb, Eight-Level NAND Flash Memory with Optimized Pulsewidth Programming,” IEEE Journal of Solid-State Circuit, Vol. 35, no. 5, pp. 682-690, May. 2000.
  5. [10] H. Kurata, N. Kobayashi, K. Kimura, “A Selective Verify Scheme for Achieving a 5-MB/s Program Rate in 3-bit/cell Flash Memories,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 166-167, Jun. 2000.
  6. [11] T. N. Blalock, R. C. Jaeger, “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier,” IEEE Journal of Solid-State Circuit, Vol. 26, no. 4, pp. 542-548, Apr. 1991.
  7. [12] S. Sundaram, P. Elakkumanan, R. Sridhar, “High Speed Robust Current Sense Amplifier for Nanoscale Memories:- A Winner Take All approach,” International Conference on VLSI Design, Held jointly with 5th Internation Conference on Embedded Systems and Design, Jan. 2006.
  8. [13] C. C. Chung, H. Lin, Y. T. Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories” IEEE Journal of Solid-State Circuits, Vol. 40, no. 2, pp. 515-522, Feb 2005.
  9. [15] S. Gregori, A. Cabrini, O. Khouri, G. Torelli, “On-Chip Error Correcting Techniques for New-Generation Flash Memories,” Proceedings of the IEEE, Vol. 91, no. 4, pp. 602-616, Apr 2003.
  10. [17] C. k. Yuen, “The Separability of Gray Code,”IEEE Transactions on Information Theory, Vol. 20, no. 5, pp. 668, Sep 1974.
  11. [1] R. Verma, “Flash memory quality and reliability issues,” Memory technology, Design and Testing, Records of the IEEE International Workshop on, pp. 32-36,Aug. 1996.
  12. [2] G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories,” Springer pp. 313-314, 2005
  13. [4] 沈祐民 “Multilevel Sensing and Verifying Circuits for Flash Memory” 2004年碩士論文,中興大學。
  14. [5] B. Ricco, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, A. Modelli, “Nonvolatile multilevel memories for digital application,” Proceedings of the IEEE, vol. 8, no.12, pp.2399-2423, Dec. 1998.
  15. [9] C. C. chung, H. Lin, Y. M. Shen, Y. T. Lin “A Multilevel Sensing and Program verifying Scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, pp.267
  16. -270, Apr. 2005.
  17. [14] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash Memory Cells-An Overview,” Proceedings of the IEEE, VOL. 85, no. 8, pp. 1248-1271, Aug 1997.
  18. [16] S. Gregori, O. Khouri, R. Micheloni, G. Torelli “An Error Control Code Scheme for Multilevel Flash Memories,” IEEE International Workshop on Memory Technology, Design and Testing, pp. 45-49, Aug. 2001.
Times Cited
  1. 葉宗翰(2011)。一種使用交錯式排列提升多值快閃記憶體可靠度的方法。中興大學資訊科學與工程學系所學位論文。2011。1-36。