以場效可規劃邏輯閘陣列為基礎之三階變頻器的研製

Implementation of Three-Level Inverters using Field Programmable Gate Array

黃仲鑫(Chung-Hsin Huang)

指導教授 ： 賴炎生

國立臺北科技大學/機電學院/機電整合研究所/碩士(2007年)

摘要

本論文之主要目的為研製一使用場效可規劃邏輯閘陣列實現具有中性點電壓控制的三階變頻器。由於二極體箝位式三階變頻器中有直流鏈上下電容電壓不平衡的問題，所以需要控制中性點電壓平衡以減少輸出的電壓與電流諧波。實驗結果顯示以場效可規劃邏輯閘陣列(Field Programmable Gate Array, FPGA)可實現中性點電壓平衡之三階變頻驅動器。
本文利用Matlab® /Simulink®所建立之控制理論模擬系統分析，實作部分採用場效可規劃邏輯陣列晶片作為控制核心，負載為三相感應馬達，控制法則使用空間向量脈波寬度調變（Space Vector Pulse Width Modulation, SVPWM）技術控制12組變頻器控制訊號，並回授上下電容電壓差與控制因子補償中性點電壓偏移的問題。系統模擬與實驗結果呈現能有夠效的控制中性點電壓平衡以及變頻控制馬達，驗證出本文控制方法的可行性。

關鍵字

場效可規劃邏輯閘陣列 ； 二極體箝位式三階變頻器 ； 空間向量調變 ； 中性點電壓平衡

並列摘要

The purpose of this thesis is to design and implement the control technique for three-level inverter using field programmable gate array (FPGA). Diode-clamped three-level inverter has the problem of neutral point voltage in balance. In this thesis a pulse-width modulation technique is presented which provides voltage balance between two DC-link capacitors and reduces the total harmonic distortion of output waveforms. The presented method requires voltage sensor only and can be realized based upon space vector modulation.
The simulation results are derived form Matlab®/Simulink® software. And the experimental results are derived from an induction motor drive controlled by field programmable gate array. It will be shown that the simulation results and experimental results agree with other very well and confirming the performance of the presented control technique for three-level inverter.

並列關鍵字

Field Programmable Gate Array ； Diode-Clamped Three-Level Inverter ； Space Vector Modulation ； Neutral Point Voltage Balance

參考文獻

[21] 周逸凱，二極體箝位式三階變頻器的研製，碩士論文，國立台北科技大學機電整合研究所，民國九十五年七月。

[22] 白昇右，具有中性點電壓平衡之二極體箝位式三階變頻器的研製，產業碩士論文，國立台北科技大學電機系研究所，民國九十六年一月。

[10] L. M. Tolbert, F. Z. Peng and T. G. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. on Industry Application, Vol. 35, No. 1, pp. 36-44, January/February 1999.

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