考量瓶頸資源之動態派工-以半導體封裝廠為例

本研究中以北台灣某公司的封裝部門為個案，該公司在派工法則運用上是以於系統內累積時間最長者優先派工。若是前後加工批量類型不同，該公司於銲線站與壓模站需作換線、換模等重新設置之動作，造成該等候線常會有批量堆疊，產生瓶頸。為了使堆疊的批量減少，將之平均分配於其他機台，卻導致堆疊情況轉為前一工作站，變成瓶頸飄移。本研究以模擬方式建構模型，提出一套考量瓶頸資源之下的動態派工法則，以期能降低案例公司瓶頸飄移之現象，減少平均生產週期時間（Cycle Time）提升平均產出（Throughput），並且設計不同實驗組合進行模擬分析，期望能找出最適合封裝產業之動態派工參數。實驗結果顯示本研究發展之動態派工法則，能有效降低平均生產週期時間，特別在壓模站改善約25％，而平均產出也能有效提升。然而在動態派工參數實驗組合中，以因子組合BL2 = 0.75天、BM1 = 4小時、BM2 = 8小時、ML2 = 6.3天，對於生產週期時間改善最佳；因子組合BL2 = 1.25天、BM1 = 8小時、BM2 = 8小時、ML2 = 2.7天，對於產出改善最佳；而因子組合分別選擇BL2介於0.75∼1.25天、BM1介於4∼8小時、BM2介於8小時與ML2為4.5天，對於封裝廠追求CT與TH將有不錯之績效。

關鍵字

半導體封裝；動態派工；瓶頸；瓶頸飄移；系統模擬

並列摘要

The research is based on a case of semiconductor assembly factory in North Taiwan. The current dispatching rule of the factory is based on accumulate cycle times only. We know that setups are needed when different package type is processed successively at bonding and molding stations. Since the setup time could last few minutes to hours, the WIP in front of bonding and molding stations fluctuates so much that two stages of processes become bottlenecks in irregular pattern. That means bottleneck shifting. The research is devoted to build the factory simulation model and develop dynamic dispatching rule considering bottleneck resources. The purpose is to decrease the situation of bottleneck shifting, reduce average cycle time, and increase throughput. In order to find the suitable were conducted parameter setting for the dynamic dispatching rule, in assembly area, different experiments. The result shows that dynamic dispatching rule can decrease average CT significantly, especially at molding station where the improvement is about 25%, and also increase average TH. When the parameters were set to BL2 as 0.75 days, BM1 as 4 hours, BM2 as 8 hours, and ML2 as 6.3 days, CT is reduced significantly. When the parameters were set to BL2 as 1.25 days, BM1 as 8 hours, BM2 as 8 hours, and ML2 as 2.7 days, TH is increased significantly. When the parameters were set to BL2 as between 0.75 and 1.25 days, BM1 as between 4 and 8 hours, BM2 as 8 hours, and ML2 as 4.5 days, CT and TH are both improved at assembly factory.

並列關鍵字

Semiconductor Assembly ； Dynamic Dispatching Rule ； Bottleneck ； Bottleneck Shifting ； System Simulation

參考文獻

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考量瓶頸資源之動態派工-以半導體封裝廠為例

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