應用於LTE發射機之低雜訊混頻器與低電壓三角積分調變器設計

Design of Low-Noise Mixer and Low Voltage Delta-Sigma Modulator for LTE Transmitter

林奐竹(Haun-Ju Lin)

指導教授 ： 陳建中 ； 黃育賢

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2011年)

摘要

本論文第一部分，提出一個高線性度、低雜訊指數的混頻器電路設計。電路的主要架構採用傳統式的吉伯特雙平衡式混頻器電路作為基本設計。傳統式的吉伯特混頻器可提升轉換增益，但其消耗功率、抗雜訊指數和線性度卻無法有效的改善。因此本電路提出增加線性度和降低雜訊指數的概念設計，藉此來改善線性度和雜訊指數的問題。電路使用台灣積體電路公司0.18微米1P6M製程來實現，晶片面積為1.054 x 0.997 mm2(包含PADs)。
本論文第二部分，提出一個低電壓D類放大器電路設計，D類放大器主要應用於音頻系統中，因此在信號頻帶內的雜訊干擾非常的注重。所以在控制迴路的部分運用三角積分調變技術，此調變技術的優點為可將信號頻寬中的雜訊移往高頻處，使頻帶內的雜訊成分成大幅降低。控制機制將音頻信號輸入至二階三角積分調變器中，使類比音頻訊號轉換成離散脈衝訊號，再經由緩衝器和非重疊時脈控制電路去控制功率電晶體，最後經由低通濾波器將音頻訊號還原。整體架構採用閉迴路式，其優點可穩定整個系統，又加上了半橋式的輸出級架構和被動元件的回授電路，因而改善了總諧波失真和信號雜訊比等問題。電路使用台灣積體電路公司0.35微米2P4M製程來實現，晶片面積為2.471 x 1.8 mm2 (包含PADs)。

關鍵字

低雜訊指數 ； 雙平衡式混頻器 ； D類放大器 ； 三角積分調變器

並列摘要

A high linearity, low noise figure of the mixer circuit design is to be proposed in the first part of this paper. Conventional double-balanced Gilbert mixer is used as a design in the main structure of the circuit. Traditional Gilbert mixer conversion gain can be increased, but its power consumption, noise figure and linearity can not be effectively improved. Therefore, this circuit is proposed to increase the linearity and lower noise figure of the conceptual design so as to improve linearity and noise figure of the problem. The proposed mixer was implemented with TSMC 0.18μm 1P6M CMOS process, and the chip area is 1.054 x 0.997 mm2 (with PADs).
Low-voltage Class D amplifier circuit is to be proposed in the second part of this paper. Class D amplifier is mainly used in audio systems, so we focus on the noise interference in the signal band. Delta-Sigma modulator is applied in the control circuit techniques, it can be moved the noise to high frequency , and make noise components reduced in the signal bandwidth. We input audio signal to the second order Delta-Sigma modulator, it can make analog audio signal into Pcm. It can control power Mos by buffer circuit and Non-overlapping circuit output. Finally, we can revert audio signal with using low-pass filter. The circuit is used closed-loop structure which can increase the stability of system. The half-bridge output stage and the feedback path can improve total harmonic distortion (THD) and signal-to-noise ratio(SNR). The proposed circuit was implemented with TSMC 0.35μm 2P4M CMOS process, and the chip area is 2.471 x 1.8 mm2 (with PADs).

並列關鍵字

Low Noise Figure ； Double Balance Mixer ； Class-D amplifier ； Delta-Sigma Modulator

參考文獻

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