適用於VDSL之12位元200MHz倍取樣率數位發射器

本論文旨在設計一適用於VDSL/VDSL2網路系統之CMOS數位發射機，其操作頻率為200MHz，並採用倍取樣率轉換技術。此發射端電路主要包含有12位元200MHz倍取樣率之數位類比轉換器，以及整合二階濾波器之電流模式全差動線驅動器兩個部份，並採用TSMC 0.18μm 1P6M CMOS製程技術來實現。 VDSL (Very High-bit-rate Digital Subscriber Line)技術使用最高達30MHz訊號頻寬，於短距離的用戶環路上，其資料傳輸可達到最高100Mbps的雙向對稱速率。其上下行傳輸的高資料速率特性，允許用戶使用電話網路的銅線傳輸，連結至最近的光纖網路節點。為了達到高資料傳輸速率的需求，本論文提出一倍取樣率架構的電流切換式12位元數位類比轉換器。其工作頻率為200MHz，於倍取樣率的工作模式下，可達到等效的400MHz資料轉換速率，其差動輸出電流訊號可達最大4095μA及最高30MHz的類比訊號頻率範圍。為了滿足VDSL標準的發射端頻譜規範，須使用發射端濾波器以濾除數位類比轉換器的高頻諧波。本論文採用的倍取樣率技術可使主要高頻諧波出現頻率向外推延兩倍，其與訊號頻寬間有更大的過渡頻帶，其結果僅需使用二階濾波器即可滿足發射端的頻譜要求。本論文使用一整合於線驅動器的二階發射端濾波器，以產生30MHz限制頻寬。線驅動器電路利用電流回授補償以及電容前饋方法，以抑制諧波失真問題，並提高線性度。本線驅動器在1.8V的供應電壓下，能驅動100Ω輸出端負載，與2Vpp的電壓訊號振幅。

關鍵字

數位類比轉換器；線驅動器；數位發射器；超高速數位用戶迴路

並列摘要

This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed double sampling-rate structure, and a fully differential current-mode line driver integrated with a 2nd-ordered transmitting filter. The digital transmitter had been fabricated with the TSMC 0.18μm 1P6M CMOS technology. VDSL (Very High-Bit Rate Digital Subscriber Line) technology permits the transmission of asymmetric and symmetric data rate up to 100Mbps for upstream and downstream direction on twisted copper pairs using a signal bandwidth up to 30MHz. It can be deployed from fiber-optic connected cabinets located near the customer premises. For such high-speed applications, the digital-to-analog converter adopts the switch-current mode architecture with a double sampling-rate operation. Under 200MHz clock frequency, the digital-to-analog converter can reach the equivalent 400MHz conversion rate. The simulation of 12-bit DAC shows that the maximum output current is 4095μA, and the conversion signal bandwidth is up to 30MHz. To conform the bandwidth requirements of VDSL/VDLS2, a transmitting filter is used after the DAC stage to filter the high-frequency harmonics. With the DAC double sampling-rate operation mode, a 2nd-ordered filter is satisfactory in the bandwidth performance. The line drive circuit integrates a transmitting filter and a current-feedback amplifier with capacitor-feedforward compensation to reach high linearity and low harmonic distortion. According to the simulation result, the output voltage of the proposed line driver is 2Vpp at differential load of 100Ω.

並列關鍵字

Digital Transmitter ； Digital-to-Analog Converter ； Line Driver ； VDSL

參考文獻

30. 李南曄，適用於十億位元乙太網路系統之10位元125MHz數位發射器，碩士論文，國立台北科技大學電機工程系研究所，台北，2009。

31. 卓儒宏，適用於VDSL之12位元數位發射器，碩士論文，國立台北科技大學電機工程系研究所，台北，2011。

20. L. Jinup, N. Sungwon, K. Kwangoh, and C. Joongho, “A 3.3-V ISDN U-Interface Line Driver With a New IQ-Control Circuit,” IEEE Journal of Solid-State Circuits, vol. 38, no. 8, August 2003, pp. 1421-1424.

4. C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE Journal of Solid-State Circuits, vol. 33, December 1998, pp. 1948-1958.

1. D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997.

國際替代計量

適用於VDSL之12位元200MHz倍取樣率數位發射器

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