熱載子導致深次微米及奈米MOSFET劣化之研究

熱載子(hot carrier)造成MOSFET劣化的問題，雖前人已有大量的研究，但隨著MOSFET的縮小至深次微米及奈米尺度，加上MOSFET在高溫操作的機會增加，使得MOSFET因熱載子而劣化的現象，呈現許多與以往不一樣的行為，本論文的重點即在一方面揭示這些新的現象，一方面找出這些新現象的機制及數學模式。本論文首先討論基底電流(substrate current)對溫度在不同汲極電壓(drain voltage)有不同依附性的問題，解開所謂轉換點(transition point)的未解問題，並為基底電流建立新的數學模式，再以實例證明，用基底電流監測熱載子可靠度已失其準確性。本論文接著探討熱載子加壓測試MOSFET中，最惡劣條件的問題，經多次實驗證明，深次微米及奈米的MOSFET其熱載子加壓測試中，最惡劣條件已由DAHC(drain avalanche hot carrier)轉至CHC(channel hot carrier)，且由低溫轉為高溫。對pMOSFET言，實驗也顯示高溫之CHC的劣化較NBTI(negative biased temperature instability)來的嚴重，論文中也找出其形成機制主要是介面電荷(interface trapped charges)所造成，並推導其壽命方程式。論文最後一個主題是熱載子導致MOSFET對匹配失序(mismatch)的問題，經實驗證明熱載子導致MOSFET劣化的同時，也會使電晶體對的匹配失序更嚴重，二者呈現正比率的關係，推論其機制應是介面電荷隨機的陷入有關。

關鍵字

熱載子； NBTI ； MOSFET ；基底電流；最惡劣加壓條件；匹配失序

並列摘要

As the MOSFETs shrink into deep submicron and nanometer regimes and most of their operations are unavoidable in high temperature, hot-carrier (HC) induced MOSFET degradation has revealed many phenomena different from the past. Therefore, although HC related issues have been studied by many researchers, it is still valuable to clear up all these new phenomena, to find out the behind mechanisms and to establish their mathematical models. In this work, the problem of substrate current exhibiting different temperature dependences at different drain voltages is investigated first. The unsolved so-call “transition point” is cleared up and a new mathematical model for substrate current is proposed. With the evidence from experiments, using the substrate current to monitor the severity of HC effect is lost its accuracy. The next problem focused in this work is the most critical stress mode that should be employed in the HC reliability test. Through many experiments, it is undoubtedly proved that the most critical stress mode has switched from DAHC (drain avalanche HC) to CHC (channel HC) mode and from low to high temperature. For pMOSFETs, it also reveals that their degradation at CHC mode is more severe than that stressed at NBTI (negative biased temperature instability) mode. As for the degradation mechanism, it is found that the interface trapped charges should be the principle culprits. In addition, lifetime models are also derived to correspond with the switch of the stress mode. The last subject of this dissertation is the MOSFET mismatches induced by the HC effects. This work found that, as the HC degrading the MOSFETs, it also degenerates the matching of MOSFETs’ properties. The experiment results reveal that the severity of HC effects and their mismatches have proportional relationship. The degeneration mechanism is inferred to be the random generation and spatial distribution of interface trapped charges.

並列關鍵字

Hot carrier ； NBTI ； MOSFET ； substrate current ； most critical stress condition ； mismatch

參考文獻

[1.8] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation－model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, 1985, pp. 295-305.

[2.8] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation－model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, 1985, pp. 295-305.

[4.14] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan and K. W. Terrill, “Hot-electron-induced MOSFET degradation－model, monitor, and improvement,” IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, 1985, pp. 295-305.

[1.3] K. Xiu and M. Ketchen, “Thermal modeling of a small extreme power density macro on a high power density microprocessor chip in the presence of realistic packaging and interconnect structure,” Electronic Components and Technology Conf., 2004, pp. 918-923.

[1.4] J. Ahn, H. Kim, T. Kim, H. Shin, Y. Kim, D. Lim, J. Kim, U. Chung, S. Lee and K. Suh, “1GHz microprocessor integration with high performance transistor and low RC delay,” IEDM Tech. Dig., 1999, pp. 683-686.

國際替代計量

熱載子導致深次微米及奈米MOSFET劣化之研究

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