Title

快速暫態響應之電源管理積體電路的設計與實現

Translated Titles

Design and Implementation of Fast Transient Power Management ICs

Authors

林宏志

Key Words

電源管理積體電路 ; 直直流轉換器 ; 低壓降線性穩壓器 ; power management ICs ; LDO ; buck converter

PublicationName

清華大學電機工程學系所學位論文

Volume or Term/Year and Month of Publication

2010年

Academic Degree Category

博士

Advisor

張慶元

Content Language

英文

Chinese Abstract

動態電壓調節技術是手持式電子產品裡用來管理電源與性能最佳化的一個非常有效的解決方案。在本論文裡,首先提出一個整合式IC化,具有適應性開啟時間之超快速電流模式降壓型直-直流轉換器電路。本論文所提出之架構可以在穩態操作的時候依照輸入與輸出電壓去動態調整開關時間用以維持固定的切換頻率;在暫態的時候可以瞬時的改變切換頻率去維持快速的暫態響應。使用本論文所提出之架構,直-直流轉換器可以同時實現快速暫態響應與固定的切換頻率。IC量測結果呈現本論文所提出之直-直流轉換器可以在整個操作範圍裡面保持5% 切換頻率誤差。在負載電阻為10 Ω時,參考電壓追蹤速度分別為11.3 μs/V (輸出電壓從0.5追蹤到2.0 V) 與 13.3 μs/V (輸出電壓從2.0追蹤到0.5 V)。此外在50 mA與500 mA負載變動時暫態響應的回復時間皆低於15 μs。這樣的暫態響應速度比現有文獻裡面的直-直流轉換器都還快。 低壓降線性穩壓器是另一個在電源管理裡面非常重要的電路。穩定性是線性穩壓器設計時非常重要的考量之一。因此在本論文第二部份,提出了一個應用於解決線性穩壓器穩定性問題的主動式頻率補償電路。本電路可以解決穩定性的問題,且不需要依賴輸出電容的等效電阻。跟傳統的補償電路比較,本論文所提之電路可以大大的增進有效的電流乘積倍數達十倍以上,且不需消耗額外的功率。本電路可以產生一個低頻的零點,而且把寄生的極點推到更高頻去,因此所提出之穩壓器的頻寬可以大大的提升。此外穩壓器所需要的晶片電容值也可以從5 pF降低至0.4 p。本IC已於TSMC 0.35-μm process 成功的實現。在輸出電流150 mA的情況下整體電路僅需要27 μA之電流消耗,且壓降電壓為200 mV。實驗結果呈現出本論文電路暫態響應跟應用傳統補償電路之穩壓器相比快上十倍。

English Abstract

Dynamic voltage scheduling (DVS) technique is an effective solution to manage the power for performance-power optimization in portable electronic devices. In this thesis, a monolithic ultra-fast current-mode adaptive on-time buck converter for DVS applications is presented firstly. The proposed technique can dynamically adjust the turn-on time of power switches according to the changes of input voltage and output voltage in steady-state operation and can change switching cycles instantaneously in transient operation. With the proposed control scheme, the dc-dc converters can accomplish both fast transient response and the capability of mitigating the switching-frequency variation. Experimental results show that the proposed converter can keep the switching-frequency constant at 650 kHz to within +-5% over the entire operation range. With a load resistor of 10 Ω, the reference tracking speeds are 11.3 μs/V for a 1.5 V step-up output change and 13.3 μs/V for a 1.5V step-down output change, respectively. The recovery times for a step load change between 50 mA to 500 mA are less than 15 μs. The transient performance is faster than the exiting counterparts. Linear low drop-out (LDO) regulator is another fundamental block of the power management circuit. The stability of the LDO is the most significant concern. Thus, an active frequency compensation circuit for low dropout regulators (LDOs) is presented in the second part. Compared with the conventional compensation scheme, the proposed circuit can greatly boost the effective current multiplication factor by at least one order of magnitude without increasing any power consumption. The proposed circuit can generate an internal lower frequency zero and push parasitic poles toward extremely high frequency such that the loop bandwidth can be extended drastically. The required on-chip capacitance is reduced to 0.4 pF, comparing to 5 pF in the conventional compensation scheme. Implemented in a 0.35-μm 2P4M CMOS process, the LDO with the proposed active frequency compensation circuit consumes 27 μA ground current at 150 mA maximum output current with a dropout voltage of 200 mV. Experimental results show that the proposed LDO structure has achieved only 10% settling time of the conventional compensation scheme.

Topic Category 電機資訊學院 > 電機工程學系所
工程學 > 電機工程
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